Debug Interface

5.8Debug Communications Channel

The ARM7TDMI processor EmbeddedICE Logic contains a DCC to pass information between the target and the host debugger. This is implemented as coprocessor 14 (CP14).

The DCC comprises:

•a 32-bit communications data read register

•a 32-bit wide communications data write register

•a 6-bit communications control register for synchronized handshaking between the processor and the asynchronous debugger.

These registers are located in fixed locations in the EmbeddedICE Logic register map, as shown in Figure B-7 on page B-41, and are accessed from the processor using MCR and MRC instructions to coprocessor 14.

The following sections describe:

•DCC registers

•Communications through the DCC on page 5-17.

5.8.1DCC registers

The DCC control register is read-only. It controls synchronized handshaking between the processor and the debugger. The control register format is shown in Figure 5-6.

The function of each register bit is as follows:

From the point of view of the debugger, the registers are accessed through scan chain 2 in the usual way. From the point of view of the processor, these registers are accessed through coprocessor register transfer instructions.

Use the instructions listed in Table 5-1 to access the DCC registers.

Because the Thumb instruction set does not contain coprocessor instructions, you are advised to access this data through SWI instructions when in Thumb state.

5.8.2Communications through the DCC

You can send and receive messages through the DCC. The following sections describe:

•Sending a message to the debugger

•Receiving a message from the debugger on page 5-18

•Interrupt driven use of the DCC on page 5-18.

Sending a message to the debugger

When the processor has to send a message to the debugger, it must check that the communications data write register is free for use by finding out if the W bit of the debug communications control register is clear.

Debug Interface

The processor reads the DCC control register to check status of the bit 1:

•If the W bit is clear then the communications data write register is clear.

•If the W bit is set, previously written data has not been read by the debugger. The processor must continue to poll the control register until the W bit is clear.

As the data transfer occurs from the processor to the DCC data write register, the W bit is set in the DCC control register. When the debugger polls this register it sees a synchronized version of both the R and W bit. When the debugger sees that the W bit is set, it can read the DCC data write register and scan the data out. The action of reading this data register clears the W bit of the DCC control register. At this point, the communications process can begin again.

Receiving a message from the debugger

Transferring a message from the debugger to the processor is similar to sending a message to the debugger. In this case, the debugger polls the R bit of the DCC control register:

•if the R bit is clear, the DCC data read register is free and data can be placed there for the processor to read

•if the R bit is set, previously deposited data has not yet been collected, so the debugger must wait.

When the DCC data read register is free, data is written there using the JTAG interface. The action of this write sets the R bit in the DCC control register.

The processor polls the DCC control register. If the R bit is set, there is data that can be read using an MRC instruction to coprocessor 14. The action of this load clears the R bit in the DCC control register. When the debugger polls this register and sees that the R bit is clear, the data has been taken and the process can now be repeated.

Interrupt driven use of the DCC

An alternative, and potentially more efficient, method to polling the debug communications control register is to use the COMMTX and COMMRX outputs from the ARM7TDMI processor. You can use these outputs to interrupt the processor when:

•a word is available to be read from the DCC data read register

•the DCC data write register is empty and available for use.

These outputs are usually connected to the system interrupt controller, that drives the nIRQ and nFIQ ARM7TDMI processor inputs.