Debug Interface

5.4ARM7TDMI core clock domains

The ARM7TDMI clocks are described in Clocks on page 5-2.

This section describes:

•Clock switch during debug

•Clock switch during test on page 5-11.

5.4.1Clock switch during debug

When the ARM7TDMI processor enters debug state, it switches automatically from MCLK to DCLK, it then asserts DBGACK in the HIGH phase of MCLK. The switch between the two clocks occurs on the next falling edge of MCLK. This is shown in Figure 5-4.

The core is forced to use DCLK as the primary clock until debugging is complete. On exit from debug, the core must be allowed to synchronize back to MCLK. This must be done by the debugger in the following sequence:

1.The final instruction of the debug sequence is shifted into the data bus scan chain and clocked in by asserting DCLK.

2.RESTART is clocked into the TAP instruction register.

The core now automatically resynchronizes back to MCLK and starts fetching instructions from memory at MCLK speed.

See Exit from debug state on page B-26.

MCLK

DBGACK

DCLK

ECLK

Multiplexer switching point

Figure 5-4 Clock switching on entry to debug state

Debug Interface

5.4.2Clock switch during test

When serial test patterns are being applied to the ARM7TDMI core through the JTAG interface, the processor must be clocked using DCLK, MCLK must be held LOW.

Entry into test is less automatic than debug and you must take care to prevent spurious clocking on the way into test.

The TAP controller can now be used to serially test the processor. If scan chain 0 and INTEST are selected, DCLK is generated while the state machine is in the RUN-TEST/IDLE state. During EXTEST, DCLK is not generated.

On exit from test, RESTART must be selected as the TAP controller instruction. When this is done, MCLK can be resumed. After INTEST testing, you must take care to ensure that the core is in a sensible state before reverting to normal operation. The safest ways to do this is are by using one of the following:

•select RESTART, then cause a system reset

•insert MOV PC, #0 into the instruction pipeline before reverting.