Debug Interface

5.1About the debug interface

The ARM7TDMI processor debug interface is based on IEEE Std. 1149.1 - 1990, Standard Test Access Port and Boundary-Scan Architecture. Refer to this standard for an explanation of the terms used in this chapter and for a description of the Test Access Port (TAP) controller states. A flow diagram of the TAP controller state transitions is provided in Figure B-2 on page B-5.

The ARM7TDMI processor contains hardware extensions for advanced debugging features. These make it easier to develop application software, operating systems and the hardware itself.

The debug extensions enable you to force the core into debug state. In debug state, the core is stopped and isolated from the rest of the system. This allows the internal state of the core and the external state of the system, to be examined while all other system activity continues as normal. When debug has completed, the debug host restores the core and system state, program execution resumes.

5.1.1Stages of debug

A request on one of the external debug interface signals, or on an internal functional unit known as the EmbeddedICE Logic, forces the ARM7TDMI processor into debug state. The events that activate debug are:

•a breakpoint, an instruction fetch

•a watchpoint, a data access

•an external debug request.

The internal state of the ARM7TDMI processor is then examined using a JTAG-style serial interface. This allows instructions to be inserted serially into the core pipeline without using the external data bus. So, for example, when in debug state, a Store Multiple (STM) can be inserted into the instruction pipeline and this exports the contents of the ARM7TDMI core registers. This data can be serially shifted out without affecting the rest of the system.

5.1.2Clocks

The ARM7TDMI core has two clocks:

•MCLK is the memory clock

•DCLK is an internal debug clock, generated by the test clock, TCK.

During normal operation, the core is clocked by MCLK and internal logic holds DCLK LOW.

Debug Interface

When the ARM7TDMI processor is in the debug state, the core is clocked by DCLK under control of the TAP state machine and MCLK can free run. The selected clock is output on the signal ECLK for use by the external system.

Note

nWAIT has no effect if the CPU core is being debugged and is running from DCLK.