Coprocessor Interface

4.6If you are not using an external coprocessor

If you are implementing a system that does not include any external coprocessors, you must tie both CPA and CPB HIGH. This indicates that no external coprocessors are present in the system. If any coprocessor instructions are received, they take the undefined instruction trap so that they can be emulated in software if required. The internal coprocessor, CP14, can still be used.

The coprocessor outputs from the ARM7TDMI processor are usually left unconnected but these outputs can be used in other parts of a system as follows:.

•nCPI

•nOPC

•TBIT.

Coprocessor Interface

4.7Undefined instructions

Undefined instructions are treated by the ARM7TDMI processor as coprocessor instructions. All coprocessors must be absent, CPA and CPB must be HIGH, when an undefined instruction is presented. The ARM7TDMI processor takes the undefined instruction trap.

For undefined instructions to be handled correctly, any coprocessors in a system must give the absent response (CPA and CPB HIGH) to an undefined instruction. This allows the core to take the undefined instruction exception.

The coprocessor must check bit 27 of the instruction to differentiate between the following instruction types:

•undefined instructions have 0 in bit 27

•coprocessor instructions have 1 in bit 27.

Coprocessor instructions are not supported in the Thumb instruction set but undefined instructions are. All coprocessors must monitor the state of the TBIT output from ARM7TDMI core. When the ARM7TDMI core is in Thumb state, coprocessors must drive CPA and CPB HIGH, and the instructions seen on the data bus must be ignored. In this way, coprocessors do not execute Thumb instructions in error, and all undefined instructions are handled correctly.

Coprocessor Interface

4.8Privileged instructions

The output signal nTRANS allows the implementation of coprocessors, or coprocessor instructions, that can only be accessed from privileged modes. The signal meanings are given in Table 4-4.

Table 4-4 Mode identifier signal meanings (nTRANS)

If used, the nTRANS signal must be sampled at the same time as the coprocessor instruction is fetched and is used in the coprocessor pipeline Decode stage.

Note

If a User mode process, with nTRANS LOW, tries to access a coprocessor instruction that can only be executed in a privileged mode, the coprocessor responds with CPA and CPB HIGH. This causes the ARM7TDMI processor to take the undefined instruction trap.

Coprocessor Interface