Coprocessor Interface

4.4Coprocessor interface handshaking

Coprocessor interface handshaking is described as follows:

•The coprocessor

•The ARM7TDMI processor on page 4-7

•Coprocessor signaling on page 4-7

•Consequences of busy-waiting on page 4-8

•Coprocessor register transfer instructions on page 4-9

•Coprocessor data operations on page 4-10

•Coprocessor load and store operations on page 4-10.

The ARM7TDMI core and any coprocessors in the system perform a handshake using the signals shown in Table 4-2.

Table 4-2 Handshaking signals

These signals are explained in more detail in Coprocessor signaling on page 4-7.

4.4.1The coprocessor

The coprocessor decodes the instruction currently in the Decode stage of its pipeline, and checks whether that instruction is a coprocessor instruction. A coprocessor instruction contains a coprocessor number that matches the coprocessor ID of the coprocessor.

If the instruction currently in the Decode stage is a relevant coprocessor instruction:

1.The coprocessor attempts to execute the instruction.

2.The coprocessor handshakes with the ARM7TDMI core using CPA and CPB.

Note

The coprocessor can drive CPA and CPB as soon as it decodes the instruction. It does not have to wait for nCPI to be LOW but it must not commit to execute the instruction until nCPI has gone LOW.

Coprocessor Interface

4.4.2The ARM7TDMI processor

Coprocessor instructions progress down the ARM7TDMI core pipeline in step with the coprocessor pipeline. A coprocessor instruction is executed if the following are true:

1.The coprocessor instruction has reached the Execute stage of the pipeline. It might not if it is preceded by a branch.

2.The ARM7TDMI processor cannot execute the instruction because the instruction is in the coprocessor or undefined part of the instruction set.

3.The instruction has passed its conditional execution tests.

If all these requirements are met, the ARM7TDMI core signals by taking nCPI LOW, this commits the coprocessor to the execution of the coprocessor instruction.

4.4.3Coprocessor signaling

The coprocessor responses are listed in Table 4-3.

Coprocessor Interface

MCLK

Coprocessor

busy waiting

Figure 4-1 Coprocessor busy-wait sequence

CPA and CPB are ignored by the ARM7TDMI processor when it does not have a undefined or coprocessor instruction in the Execute stage of the pipeline.

A summary of coprocessor signaling is listed in Table 4-3 on page 4-7.

4.4.4Consequences of busy-waiting

A busy-waited coprocessor instruction can be interrupted. If a valid FIQ or IRQ occurs and the appropriate bit is clear in the CSPR, then the ARM7TDMI processor abandons the coprocessor instruction, and signals this by taking nCPI HIGH. A coprocessor that is capable of busy-waiting must monitor nCPI to detect this condition. When the ARM7TDMI core abandons a coprocessor instruction, the coprocessor also abandons the instruction, and continues tracking the ARM7TDMI processor pipeline.

Coprocessor Interface

Caution

It is essential that any action taken by the coprocessor while it is busy-waiting is idempotent. This means that the actions taken by the coprocessor must not corrupt the state of the coprocessor, and must be repeatable with identical results. The coprocessor can only change its own state once the instruction has been executed.

The ARM7TDMI processor usually returns from processing the interrupt to retry the coprocessor instruction. Other coprocessor instructions can be executed before the interrupted instruction is executed again.

4.4.5Coprocessor register transfer instructions

The coprocessor register transfer instructions, MCR and MRC, are used to transfer data between a register in the ARM7TDMI processor register bank and a register in the coprocessor register bank. An example sequence for a coprocessor register transfer is shown in Figure 4-2.

nCPI

CPA

CPB

Figure 4-2 Coprocessor register transfer sequence