Coprocessor Interface

4.2Coprocessor interface signals

The signals used to interface the ARM7TDMI core to a coprocessor are grouped into four categories.

The clock and clock control signals are:

•MCLK

•nWAIT

•nRESET.

The pipeline following signals are:

•nMREQ

•SEQ

•nTRANS

•nOPC

•TBIT.

The handshake signals are:

•nCPI

•CPA

•CPB.

The data signals are:

•D[31:0]

•DIN[31:0]

•DOUT[31:0].

Coprocessor Interface

4.3Pipeline following signals

Every coprocessor in the system must contain a pipeline follower to track the instructions in the ARM7TDMI processor pipeline. The coprocessors connect to the configured ARM7TDMI core input data bus, D[31:0] or DIN[31:0], over which instructions are fetched, and to MCLK and nWAIT.

It is essential that the two pipelines remain in step at all times. When designing a pipeline follower for a coprocessor, the following rules must be observed:

•At reset, with nRESET LOW, the pipeline must either be marked as invalid, or filled with instructions that do not decode to valid instructions for that coprocessor.

•The coprocessor state must only change when nWAIT is HIGH, except during reset.

•An instruction must be loaded into the pipeline on the falling edge of MCLK, and only when nOPC, nMREQ, and TBIT were all LOW in the previous bus cycle.

These conditions indicate that this cycle is an ARM instruction fetch, so the new opcode must be read into the pipeline.

•The pipeline must be advanced on the falling edge of MCLK when nOPC, nMREQ and TBIT are all LOW in the current bus cycle.

These conditions indicate that the current instruction is about to complete execution, because the first action of any instruction performing an instruction fetch is to refill the pipeline.

Any instructions that are flushed from the ARM7TDMI processor pipeline:

•never signal on nCPI that they have entered execute

•are automatically replaced in the coprocessor pipeline follower by the prefetches required to refill the core pipeline.

There are no coprocessor instructions in the Thumb instruction set, and so coprocessors must monitor the state of the TBIT signal to ensure that they do not decode pairs of Thumb instructions as ARM instructions.