Coprocessor Interface

4.1About coprocessors

The ARM7TDMI core instruction set enables you to implement specialized additional instructions using coprocessors to extend functionality. These are separate processing units that are tightly coupled to the ARM7TDMI processor. A typical coprocessor contains:

•an instruction pipeline (pipeline follower)

•instruction decoding logic

•handshake logic

•a register bank

•special processing logic, with its own data path.

A coprocessor is connected to the same data bus as the ARM7TDMI processor in the system, and tracks the pipeline in the ARM7TDMI processor. This means that the coprocessor can decode the instructions in the instruction stream, and execute those that it supports. Each instruction progresses down both the ARM7TDMI core pipeline and the coprocessor pipeline at the same time.

The execution of instructions is shared between the ARM7TDMI core and the coprocessor.

The ARM7TDMI processor:

1.Evaluates the instruction type and the condition codes to determine whether the instructions are executed by the coprocessor, and communicates this to any coprocessors in the system, using nCPI.

2.Generates any addresses that are required by the instruction, including prefetching the next instruction to refill the pipeline.

3.Takes the undefined instruction trap if no coprocessor accepts the instruction. The coprocessor:

1.Decodes instructions to determine whether it can accept the instruction.

2.Indicates whether it can accept the instruction by using CPA and CPB.

3.Fetches any values required from its own register bank.

4.Performs the operation required by the instruction.

If a coprocessor cannot execute an instruction, the instruction takes the undefined instruction trap. You can choose whether to emulate coprocessor functions in software, or to design a dedicated coprocessor.

Coprocessor Interface

4.1.1Coprocessor availability

Up to 16 coprocessors can be referenced by a system, each with a unique coprocessor ID number to identify it. The ARM7TDMI core contains one internal coprocessor:

•CP14, the debug communications channel coprocessor.

Other coprocessor numbers have also been reserved. Coprocessor availability is listed in Table 4-1.

Table 4-1 Coprocessor availability

If you intend to design a coprocessor send an email with coprocessor in the subject line to info@arm.com for up-to-date information on which coprocessor numbers have been allocated.