Memory Interface

3.8Action of ARM7TDMI core in debug state

When the ARM7TDMI core is in debug state, nMREQ and SEQ are forced to indicate internal cycles. This allows the rest of the memory system to ignore the processor and function as normal. Because the rest of the system continues operation, the core ignores aborts and interrupts while in debug state.

The BIGEND signal must not be changed by the system during debug. If BIGEND changes, not only is there a synchronization problem but the programmer view of the processor changes without the knowledge of the debugger. Signal nRESET must also be held stable during debug. If nRESET is driven LOW then the state of the processor changes without the knowledge of the debugger.

When instructions are executed in debug state, all bus interface outputs, except nMREQ and SEQ, change asynchronously to the memory system. For example, every time a new instruction is scanned into the pipeline, the address bus changes. Although this is asynchronous it does not affect the system as nMREQ and SEQ are forced to indicate internal cycles regardless of what the rest of the processor is doing. The memory controller must be designed to ensure that this asynchronous behavior does not affect the rest of the system.

Memory Interface

3.9Privileged mode access

ARM Limited usually recommends that if only privileged mode access is required from a memory system then you are advised to use the nTRANS pin on the core. This signal distinguishes between User and privileged accesses.

The reason that this is recommended is that if the Operating System (OS) accesses memory on behalf of the current application then it must perform these accesses in User mode. This is achieved using the LDRT and STRT instructions that set nTRANS appropriately.

This measure avoids the possibility of a hacker deliberately passing an invalid pointer to an OS and getting the OS to access this memory with privileged access. This technique could otherwise be used by a hacker to enable the user application to access any memory locations such as I/O space.

The least significant five bits of the CPSR are also output from the core as inverted signals, nM[4:0]. These indicate the current processor mode as listed in Table 3-8.

Table 3-8 Use of nM[4:0] to indicate current processor mode

M[4:0] nM[4:0] Mode

10000 01111 User

10001 01110 FIQ

10010 01101 IRQ

10011 01100 Supervisor

10111 01000 Abort

11011 00100 Undefined

11111 00000 System

Note

The only time to use the nM[4:0] signals is for diagnostic and debug purposes.

Memory Interface

3.10Reset sequence after power up

It is good practice to reset a static device immediately on power-up, to remove any undefined conditions within the device that can otherwise combine to cause a DC path and consequently increase current consumption. Most systems are reset by using a simple RC circuit on the reset pin to remove the undefined states within devices whilst clocking the device.

During reset, the signals nMREQ and SEQ show internal cycles where the address bus continues to increment by two or four bytes. The initial address and increment values are determined by the state of the core when nRESET was asserted. They are undefined after power up.

After nRESET has been taken HIGH, the ARM core does two further internal cycles before the first instruction is fetched from the reset vector (address 0x00000000). It then takes three MCLK cycles to advance this instruction through the Fetch-Decode-Execute stages of the ARM instruction pipeline before this first instruction is executed. This is shown in Figure 3-22.

Note

nRESET must be held asserted for a minimum of two MCLK cycles to fully reset the core.

You must reset the EmbeddedICE Logic and the TAP controller as well, whether the debug features are used or are not. This is done by taking nTRST LOW for at least Tbsr, no later than nRESET.

In Figure 3-22, x, y, and z are incrementing address values.

MCLK

nRESET

D[31:0]

nMREQ

SEQ

nEXEC

Figure 3-22 Reset sequence

Memory Interface