Memory Interface

3.7Stretching access times

The ARM7TDMI processor does not contain any dynamic logic that relies on regular clocking to maintain the internal state. Therefore, there is no limit upon the maximum period for which MCLK can be stretched, or nWAIT held LOW. There are two methods available to stretch access times as described in:

•Modulating MCLK

•Use of nWAIT to control bus cycles.

Note

If you wish to use an Embedded Trace Macrocell (ETM) to obtain instruction and data trace information on a trace port then you must use the nWAIT signal to stretch access times.

3.7.1Modulating MCLK

All memory timing is defined by MCLK, and long access times can be accommodated by stretching this clock. It is usual to stretch the LOW period of MCLK, as this allows the memory manager to abort the operation if the access is eventually unsuccessful.

MCLK can be stretched before being applied to the processor, or the nWAIT input can be used together with a free-running MCLK. Taking nWAIT LOW has the same effect as stretching the LOW period of MCLK.

3.7.2Use of nWAIT to control bus cycles

The pipelined nature of the processor bus interface means that there is a distinction between clock cycles and bus cycles. nWAIT can be used to stretch a bus cycle, so that it lasts for many clock cycles. The nWAIT input allows the timing of bus cycles to be extended in increments of complete MCLK cycles:

•when nWAIT is HIGH on the falling edge of MCLK, a bus cycle completes

•when nWAIT is LOW, the bus cycle is extended by stretching the low phase of the internal clock.

nWAIT must only change during the LOW phase of MCLK.

In the pipeline, the address class signals and the memory request signals are ahead of the data transfer by one bus cycle. In a system using nWAIT this can be more than one MCLK cycle. This is illustrated in Figure 3-21 on page 3-30, which shows nWAIT being used to extend a nonsequential cycle. In the example, the first N-cycle is followed a few cycles later by another N-cycle to an unrelated address, and the address for the second access is broadcast before the first access completes.

Memory Interface

MCLK

nWAIT

nMREQ

SEQ

nRW

D[31:0]

nRAS

nCAS

Figure 3-21 Typical system timing

Note

When designing a memory controller, you are strongly advised to sample the values of nMREQ, SEQ, and the address class signals only when nWAIT is HIGH. This ensures that the state of the memory controller is not accidentally updated during an extended bus cycle.