List of Figures
ARM7TDMI Technical Reference Manual
|
Key to timing diagram conventions ............................................................................. |
xx |
Figure 1-1 |
Instruction pipeline .................................................................................................... |
1-2 |
Figure 1-2 |
ARM7TDMI processor block diagram ....................................................................... |
1-6 |
Figure 1-3 |
Main processor .......................................................................................................... |
1-7 |
Figure 1-4 |
ARM7TDMI processor functional diagram ................................................................ |
1-8 |
Figure 1-5 |
ARM instruction set formats .................................................................................... |
1-10 |
Figure 1-6 |
Thumb instruction set formats ................................................................................. |
1-19 |
Figure 2-1 |
LIttle-endian addresses of bytes and halfwords within words ................................... |
2-4 |
Figure 2-2 |
Big-endian addresses of bytes and halfwords within words ...................................... |
2-5 |
Figure 2-3 |
Register organization in ARM state ........................................................................... |
2-9 |
Figure 2-4 |
Register organization in Thumb state ..................................................................... |
2-10 |
Figure 2-5 |
Mapping of Thumb-state registers onto ARM-state registers .................................. |
2-11 |
Figure 2-6 |
Program status register format ................................................................................ |
2-13 |
Figure 3-1 |
Simple memory cycle ................................................................................................ |
3-4 |
Figure 3-2 |
Nonsequential memory cycle .................................................................................... |
3-6 |
Figure 3-3 |
Sequential access cycles .......................................................................................... |
3-7 |
Figure 3-4 |
Internal cycles ........................................................................................................... |
3-8 |
Figure 3-5 |
Merged IS cycle ........................................................................................................ |
3-9 |
Figure 3-6 |
Coprocessor register transfer cycles ....................................................................... |
3-10 |
Figure 3-7 |
Memory cycle timing ............................................................................................... |
3-10 |
Figure 3-8 |
Pipelined addresses ................................................................................................ |
3-14 |
Figure 3-9 |
Depipelined addresses ............................................................................................ |
3-15 |
Figure 3-10 |
SRAM compatible address timing ........................................................................... |
3-16 |
ARM DDI 0029G |
Copyright © 1994-2001. All rights reserved. |
xiii |
List of Figures
Figure 3-11 |
External bus arrangement ...................................................................................... |
3-17 |
Figure 3-12 |
Bidirectional bus timing ........................................................................................... |
3-18 |
Figure 3-13 |
Unidirectional bus timing ......................................................................................... |
3-18 |
Figure 3-14 |
External connection of unidirectional buses ........................................................... |
3-19 |
Figure 3-15 |
Data write bus cycle ................................................................................................ |
3-20 |
Figure 3-16 |
Data bus control circuit ........................................................................................... |
3-20 |
Figure 3-17 |
Test chip data bus circuit ........................................................................................ |
3-23 |
Figure 3-18 |
Memory access ....................................................................................................... |
3-25 |
Figure 3-19 |
Two cycle memory access ...................................................................................... |
3-26 |
Figure 3-20 |
Data replication ....................................................................................................... |
3-28 |
Figure 3-21 |
Typical system timing ............................................................................................. |
3-30 |
Figure 3-22 |
Reset sequence ...................................................................................................... |
3-33 |
Figure 4-1 |
Coprocessor busy-wait sequence ............................................................................. |
4-8 |
Figure 4-2 |
Coprocessor register transfer sequence ................................................................... |
4-9 |
Figure 4-3 |
Coprocessor data operation sequence ................................................................... |
4-10 |
Figure 4-4 |
Coprocessor load sequence ................................................................................... |
4-11 |
Figure 4-5 |
Coprocessor connections with bidirectional bus ..................................................... |
4-12 |
Figure 4-6 |
Coprocessor connections with unidirectional bus ................................................... |
4-13 |
Figure 4-7 |
Connecting multiple coprocessors .......................................................................... |
4-14 |
Figure 5-1 |
Typical debug system ............................................................................................... |
5-4 |
Figure 5-2 |
ARM7TDMI block diagram ........................................................................................ |
5-5 |
Figure 5-3 |
Debug state entry ..................................................................................................... |
5-7 |
Figure 5-4 |
Clock switching on entry to debug state ................................................................. |
5-10 |
Figure 5-5 |
ARM7TDM, TAP controller, and EmbeddedICE Logic ........................................... |
5-13 |
Figure 5-6 |
DCC control register format .................................................................................... |
5-16 |
Figure 7-1 |
General timing .......................................................................................................... |
7-4 |
Figure 7-2 |
ABE control timing .................................................................................................... |
7-6 |
Figure 7-3 |
Bidirectional data write cycle timing .......................................................................... |
7-7 |
Figure 7-4 |
Bidirectional data read cycle timing .......................................................................... |
7-8 |
Figure 7-5 |
Data bus control timing ............................................................................................. |
7-9 |
Figure 7-6 |
Output 3-state timing .............................................................................................. |
7-10 |
Figure 7-7 |
Unidirectional data write cycle timing ...................................................................... |
7-11 |
Figure 7-8 |
Unidirectional data read cycle timing ...................................................................... |
7-12 |
Figure 7-9 |
Configuration pin timing .......................................................................................... |
7-13 |
Figure 7-10 |
Coprocessor timing ................................................................................................. |
7-14 |
Figure 7-11 |
Exception timing ..................................................................................................... |
7-15 |
Figure 7-12 |
Synchronous interrupt timing .................................................................................. |
7-16 |
Figure 7-13 |
Debug timing ........................................................................................................... |
7-17 |
Figure 7-14 |
DCC output timing .................................................................................................. |
7-19 |
Figure 7-15 |
Breakpoint timing .................................................................................................... |
7-20 |
Figure 7-16 |
TCK and ECLK timing ............................................................................................. |
7-21 |
Figure 7-17 |
MCLK timing ........................................................................................................... |
7-22 |
Figure 7-18 |
Boundary scan general timing ................................................................................ |
7-23 |
Figure 7-19 |
Reset period timing ................................................................................................. |
7-24 |
Figure 7-20 |
Output enable and disable times due to HIGHZ TAP instruction ............................ |
7-25 |
Figure 7-21 |
Output enable and disable times due to data scanning .......................................... |
7-25 |
Figure 7-22 |
ALE control timing ................................................................................................... |
7-26 |
xiv |
Copyright © 1994-2001. All rights reserved. |
ARM DDI 0029G |
|
|
List of Figures |
Figure 7-23 |
APE control timing ................................................................................................... |
7-27 |
Figure B-1 |
ARM7TDMI core scan chain arrangements .............................................................. |
B-4 |
Figure B-2 |
Test access port controller state transitions .............................................................. |
B-5 |
Figure B-3 |
ID code register format ............................................................................................ |
B-14 |
Figure B-4 |
Input scan cell ......................................................................................................... |
B-17 |
Figure B-5 |
Clock switching on entry to debug state .................................................................. |
B-22 |
Figure B-6 |
Debug exit sequence .............................................................................................. |
B-28 |
Figure B-7 |
EmbeddedICE block diagram ................................................................................. |
B-41 |
Figure B-8 |
Watchpoint control value and mask format ............................................................. |
B-42 |
Figure B-9 |
Debug control register format .................................................................................. |
B-48 |
Figure B-10 |
Debug status register format ................................................................................... |
B-50 |
Figure B-11 |
Debug control and status register structure ............................................................ |
B-51 |
ARM DDI 0029G |
Copyright © 1994-2001. All rights reserved. |
xv |
List of Figures
xvi |
Copyright © 1994-2001. All rights reserved. |
ARM DDI 0029G |