Chapter 3

Memory Interface

This chapter describes the ARM7TDMI processor memory interface. It contains the following sections:

•About the memory interface on page 3-2

•Bus interface signals on page 3-3

•Bus cycle types on page 3-4

•Addressing signals on page 3-11

•Address timing on page 3-14

•Data timed signals on page 3-17

•Stretching access times on page 3-29

•Action of ARM7TDMI core in debug state on page 3-31

•Privileged mode access on page 3-32

•Reset sequence after power up on page 3-33.

Memory Interface

3.1About the memory interface

The ARM7TDMI processor has a Von Neumann architecture, with a single 32-bit data bus carrying both instructions and data. Only load, store, and swap instructions can access data from memory.

Memory Interface

3.2Bus interface signals

The signals in the ARM7TDMI processor bus interface can be grouped into four categories:

•clocking and clock control

•address class signals

•memory request signals

•data timed signals.

The clocking and clock control signals are:

•MCLK

•nWAIT

•ECLK

•nRESET.

The address class signals are:

•A[31:0]

•nRW

•MAS[1:0]

•nOPC

•nTRANS

•LOCK

•TBIT.

The memory request signals are:

•nMREQ

•SEQ.

The data timed signals are:

•D[31:0]

•DIN[31:0]

•DOUT[31:0]

•ABORT

•BL[3:0].

The ARM7TDMI processor uses both the rising and falling edges of MCLK.

Bus cycles can be extended using the nWAIT signal. This signal is described in Stretching access times on page 3-29. All other sections of this chapter describe a simple system in which nWAIT is permanently HIGH.