Programmer’s Model

2.8.7Software interrupt instruction

The Software Interrupt instruction (SWI) is used to enter Supervisor mode, usually to request a particular supervisor function. The SWI handler reads the opcode to extract the SWI function number.

A SWI handler returns by executing the following irrespective of the processor operating state:

MOVS PC, R14_svc

This action restores the PC and CPSR, and returns to the instruction following the SWI.

2.8.8Undefined instruction

When the ARM7TDMI processor encounters an instruction that neither it, nor any coprocessor in the system can handle, the ARM7TDMI core takes the undefined instruction trap. Software can use this mechanism to extend the ARM instruction set by emulating undefined coprocessor instructions.

After emulating the failed instruction, the trap handler executes the following irrespective of the processor operating state:

MOVS PC,R14_und

This action restores the CPSR and returns to the next instruction after the undefined instruction.

For more information about undefined instructions, see the ARM Architecture Reference Manual.

2.8.9Exception vectors

Table 2-4 lists the exception vector addresses. In this table, I and F represent the previous value of the IRQ and FIQ interrupt disable bits respectively in the CPSR.

Table 2-4 Exception vectors

Programmer’s Model

Table 2-4 Exception vectors (continued)

2.8.10Exception priorities

When multiple exceptions arise at the same time, a fixed priority system determines the order in which they are handled. The priority order is listed in Table 2-5.

Table 2-5 Exception priority order

Some exceptions cannot occur together:

•The undefined instruction and SWI exceptions are mutually exclusive. Each corresponds to a particular, non-overlapping, decoding of the current instruction.

•When FIQs are enabled, and a Data Abort occurs at the same time as an FIQ, the ARM7TDMI processor enters the Data Abort handler, and proceeds immediately to the FIQ vector.

A normal return from the FIQ causes the Data Abort handler to resume execution.

Data Aborts must have higher priority than FIQs to ensure that the transfer error does not escape detection. You must add the time for this exception entry to the worst-case FIQ latency calculations in a system that uses aborts to support virtual memory.