Programmer’s Model

2.7The program status registers

The ARM7TDMI processor contains a CPSR and five SPSRs for exception handlers to use. The program status registers:

•hold information about the most recently performed ALU operation

•control the enabling and disabling of interrupts

•set the processor operating mode.

The arrangement of bits is shown in Figure 2-6.

Figure 2-6 Program status register format

Note

To maintain compatibility with future ARM processors, you must not alter any of the reserved bits. One method of preserving these bits is to use a read-write-modify strategy when changing the CPSR.

The remainder of this section describes:

•Condition code flags

•Control bits on page 2-14

•Reserved bits on page 2-15.

2.7.1Condition code flags

The N, Z, C, and V bits are the condition code flags, you can set them by arithmetic and logical operations. They can also be set by MSR and LDM instructions. The ARM7TDMI processor tests these flags to determine whether to execute an instruction.

Programmer’s Model

All instructions can execute conditionally in ARM state. In Thumb state, only the Branch instruction can be executed conditionally. For more information about conditional execution, refer to the ARM Architecture Reference Manual.

2.7.2Control bits

The bottom eight bits of a PSR are known collectively as the control bits. They are the:

•interrupt disable bits

•T bit

•mode bits.

The control bits change when an exception occurs. When the processor is operating in a privileged mode, software can manipulate these bits.

Interrupt disable bits

The I and F bits are the interrupt disable bits:

•when the I bit is set, IRQ interrupts are disabled

•when the F bit is set, FIQ interrupts are disabled.

T bit

The T bit reflects the operating state:

•when the T bit is set, the processor is executing in Thumb state

•when the T bit is clear, the processor executing in ARM state.

The operating state is reflected on the external signal TBIT.

Caution

Never use an MSR instruction to force a change to the state of the T bit in the CPSR. If you do this, the processor enters an unpredictable state.

Programmer’s Model

Mode bits

Bits M[4:0] determine the processor operating mode as shown in Table 2-2. Not all combinations of the mode bits define a valid processor mode, so take care to use only the bit combinations shown.

An illegal value programmed into M[4:0] causes the processor to enter an unrecoverable state. If this occurs, apply reset.

2.7.3Reserved bits

The remaining bits in the PSRs are unused, but are reserved. When changing a PSR flag or control bits, make sure that these reserved bits are not altered. Also, make sure that your program does not rely on reserved bits containing specific values because future processors might have these bits set to 1 or 0.