List of Tables

Change history ..............................................................................................................

ii

Table 1-1

Key to tables .............................................................................................................

1-9

Table 1-2

ARM instruction summary .......................................................................................

1-11

Table 1-3

Addressing modes ..................................................................................................

1-14

Table 1-4

Operand 2 ...............................................................................................................

1-16

Table 1-5

Fields .......................................................................................................................

1-17

Table 1-6

Condition fields ........................................................................................................

1-17

Table 1-7

Thumb instruction set summary ..............................................................................

1-20

Table 2-1

Register mode identifiers ..........................................................................................

2-7

Table 2-2

PSR mode bit values ...............................................................................................

2-15

Table 2-3

Exception entry and exit ..........................................................................................

2-16

Table 2-4

Exception vectors ....................................................................................................

2-21

Table 2-5

Exception priority order ...........................................................................................

2-22

Table 3-1

Bus cycle types .........................................................................................................

3-5

Table 3-2

Burst types ................................................................................................................

3-7

Table 3-3

Significant address bits ...........................................................................................

3-12

Table 3-4

nOPC ......................................................................................................................

3-12

Table 3-5

nTRANS encoding ..................................................................................................

3-13

Table 3-6

Tristate control of processor outputs .......................................................................

3-21

Table 3-7

Read accesses ........................................................................................................

3-27

Table 3-8

Use of nM[4:0] to indicate current processor mode ................................................

3-32

Table 4-1

Coprocessor availability ............................................................................................

4-3

Table 4-2

Handshaking signals .................................................................................................

4-6

ARM DDI 0029G

Copyright © 1994-2001. All rights reserved.

ix

Table 4-3

Summary of coprocessor signaling ...........................................................................

4-7

Table 4-4

Mode identifier signal meanings (nTRANS) ............................................................

4-17

Table 5-1

DCC register access instructions ............................................................................

5-17

Table 6-1

Branch instruction cycle operations ..........................................................................

6-4

Table 6-2

Thumb long branch with link .....................................................................................

6-5

Table 6-3

Branch and exchange instruction cycle operations ..................................................

6-6

Table 6-4

Data operation instruction cycles ..............................................................................

6-8

Table 6-5

Multiply instruction cycle operations .........................................................................

6-9

Table 6-6

Multiply accumulate instruction cycle operations ......................................................

6-9

Table 6-7

Multiply long instruction cycle operations ...............................................................

6-10

Table 6-8

Multiply accumulate long instruction cycle operations ............................................

6-10

Table 6-9

Load register instruction cycle operations ..............................................................

6-12

Table 6-10

MAS[1:0] signal encoding .......................................................................................

6-13

Table 6-11

Store register instruction cycle operations ..............................................................

6-14

Table 6-12

Load multiple registers instruction cycle operations ...............................................

6-15

Table 6-13

Store multiple registers instruction cycle operations ...............................................

6-17

Table 6-14

Data swap instruction cycle operations ..................................................................

6-18

Table 6-15

Software Interrupt instruction cycle operations .......................................................

6-19

Table 6-16

Coprocessor data operation instruction cycle operations .......................................

6-20

Table 6-17

Coprocessor data transfer instruction cycle operations ..........................................

6-21

Table 6-18

coprocessor data transfer instruction cycle operations ...........................................

6-23

Table 6-19

Coprocessor register transfer, load from coprocessor ............................................

6-25

Table 6-20

Coprocessor register transfer, store to coprocessor ...............................................

6-26

Table 6-21

Undefined instruction cycle operations ...................................................................

6-27

Table 6-22

Unexecuted instruction cycle operations ................................................................

6-28

Table 6-23

ARM instruction speed summary ............................................................................

6-29

Table 7-1

General timing parameters .......................................................................................

7-5

Table 7-2

ABE control timing parameters .................................................................................

7-6

Table 7-3

Bidirectional data write cycle timing parameters .......................................................

7-7

Table 7-4

Bidirectional data read cycle timing parameters .......................................................

7-8

Table 7-5

Data bus control timing parameters ..........................................................................

7-9

Table 7-6

Output 3-state time timing parameters ...................................................................

7-10

Table 7-7

Unidirectional data write cycle timing parameters ..................................................

7-11

Table 7-8

Unidirectional data read cycle timing parameters ...................................................

7-12

Table 7-9

Configuration pin timing parameters .......................................................................

7-13

Table 7-10

Coprocessor timing parameters ..............................................................................

7-14

Table 7-11

Exception timing parameters ..................................................................................

7-15

Table 7-12

Synchronous interrupt timing parameters ...............................................................

7-16

Table 7-13

Debug timing parameters .......................................................................................

7-17

Table 7-14

DCC output timing parameters ...............................................................................

7-19

Table 7-15

Breakpoint timing parameters .................................................................................

7-20

Table 7-16

TCK and ECLK timing parameters .........................................................................

7-21

Table 7-17

MCLK timing parameters ........................................................................................

7-22

Table 7-18

Boundary scan general timing parameters .............................................................

7-23

Table 7-19

Reset period timing parameters ..............................................................................

7-24

Table 7-20

Output enable and disable timing parameters ........................................................

7-25

Table 7-21

ALE address control timing parameters ..................................................................

7-26

x

Copyright © 1994-2001. All rights reserved.

ARM DDI 0029G

List of Tables

Table 7-22

APE control timing parameters ...............................................................................

7-27

Table 7-23

AC timing parameters used in this chapter .............................................................

7-28

Table A-1

Transistor sizes .........................................................................................................

A-2

Table A-2

Signal types ...............................................................................................................

A-2

Table A-3

Signal Descriptions ...................................................................................................

A-3

Table B-1

Public instructions .....................................................................................................

B-9

Table B-2

Scan chain number allocation .................................................................................

B-16

Table B-3

Scan chain 0 cells ...................................................................................................

B-33

Table B-4

Scan chain 1 cells ...................................................................................................

B-37

Table B-5

Function and mapping of EmbeddedICE registers .................................................

B-40

Table B-6

MAS[1:0] signal encoding .......................................................................................

B-43

Table B-7

Interrupt signal control .............................................................................................

B-48

ARM DDI 0029G

Copyright © 1994-2001. All rights reserved.

xi

xii

Copyright © 1994-2001. All rights reserved.

ARM DDI 0029G