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Programmer’s Model

2.3Memory formats

The ARM7TDMI processor views memory as a linear collection of bytes numbered in ascending order from zero. For example:

bytes zero to three hold the first stored word

bytes four to seven hold the second stored word.

The ARM7TDMI processor is bi-endian and can treat words in memory as being stored in either:

Little-endian.

Big-Endian on page 2-5

Note

Little-endian is traditionally the default format for ARM processors.

The endian format of a CPU dictates where the most significant byte or digits must be placed in a word. Because numbers are calculated by the CPU starting with the least significant digits, little-endian numbers are already set up for the processing order.

Endian configuration has no relevance unless data is stored as words and then accessed in smaller sized quantities (halfwords or bytes).

2.3.1Little-endian

In little-endian format, the lowest addressed byte in a word is considered the least-significant byte of the word and the highest addressed byte is the most significant. So the byte at address 0 of the memory system connects to data lines 7 through 0.

For a word-aligned address A, Figure 2-1 shows how the word at address A, the halfword at addresses A and A+2, and the bytes at addresses A, A+1, A+2, and A+3 map on to each other when the core is configured as little-endian.

31

24

23

16

15

8

7

0

 

 

 

Word at address A

 

 

 

 

 

 

 

 

 

 

 

Halfword at address A+2

 

 

Halfword at address A

 

 

 

 

 

Byte at address A+3

Byte at address A+2

Byte at address A+1

 

Byte at address A

 

 

 

 

 

 

 

 

Figure 2-1 LIttle-endian addresses of bytes and halfwords within words

2-4

Copyright © 1994-2001. All rights reserved.

ARM DDI 0029G

Programmer’s Model

2.3.2Big-Endian

In big-endian format, the ARM7TDMI processor stores the most significant byte of a word at the lowest-numbered byte, and the least significant byte at the highest-numbered byte. So the byte at address 0 of the memory system connects to data lines 31 through 24.

For a word-aligned address A, Figure 2-2 shows how the word at address A, the halfword at addresses A and A+2, and the bytes at addresses A, A+1, A+2, and A+3 map on to each other when the core is configured as big-endian.

31

24

23

16

15

8

7

0

 

 

 

Word at address A

 

 

 

 

 

 

 

 

 

 

 

 

Halfword at address A

 

 

Halfword at address A+2

 

 

 

 

 

Byte at address A

Byte at address A+1

Byte at address A+2

Byte at address A+3

 

 

 

 

 

 

 

 

Figure 2-2 Big-endian addresses of bytes and halfwords within words

ARM DDI 0029G

Copyright © 1994-2001. All rights reserved.

2-5

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