Fundamentals of Microelectronics

where VCM = 1 V denotes the input common-mode level.

(a)If V0 = 2 mV, plot the output waveforms (as a function of time).

(b)If V0 = 50 mV, determine the time t1 at which one transistor carries 95% of the tail current. Plot the output waveforms.

25.The study in Example 10.9 suggests that a differential pair can convert a sinusoid to a square wave. Using the circuit parameters given in Problem 24, plot the output waveforms if V0 = 80 mV or 160 mV. Explain why the output square wave becomes “sharper” as the input amplitude increases.

26.In Problem 25, estimate the slope of the output square waves for V0 = 80 mV or 160 mV if

! = 2 (100 MHz).

27.Repeat the small-signal analysis of Fig. 10.15 for the circuit shown in Fig. 10.66. (First, prove that P is still a virtual ground.)

Figure 10.66

28.Using a small-signal model and including the output resistance of the transistors, prove that Eq. (10.86 holds in the presence of the Early effect.

29.In Fig. 10.67, IEE = 1 mA and VA = 5 V. Calculate the voltage gain of the circuit. Note that the gain is independent of the tail current.

P

I EE

Figure 10.67

30.Consider the circuit shown in Fig. 10.68, where IEE = 2 mA, VA;n = 5 V VA;p = 4 V. What value of R1 = R2 allows a voltage gain of 50?

31.The circuit of Fig. 10.68 must provide a gain of 50 with R1 = R2 = 5 k . If VA;n = 5 V and VA;p = 4 V, calculate the required tail current.

Figure 10.68

32.Assuming perfect symmetry and VA < 1, compute the differential voltage gain of each stage depicted in Fig. 10.69.

Figure 10.69

33.Assuming perfect symmetry and VA < 1, compute the differential voltage gain of each stage depicted in Fig. 10.70. You may need to compute the gain as Av = ,GmRout in some cases.

34.Consider the differential pair illustrated in Fig. 10.71. Assuming perfect symmetry and VA =

1,

(a)Determine the voltage gain.

(b)Under what condition does the gain become independent of the tail currents? This is an example of a very linear circuit because the gain does not vary with the input or output signal levels.

Figure 10.71

35.Consider the MOS differential pair of Fig. 10.24. What happens to the tail node voltage if

(a) the width of M1 and M2 is doubled, (b) ISS is doubled, (c) the gate oxide thickness is doubled.

36.In the MOS differential pair of Fig. 10.24, VCM = 1 V, ISS = 1 mA, and RD = 1 k . What is the minimum allowable supply voltage if the transistors must remain in saturation? Assume VT H;n = 0:5 V.

37.The MOS differential pair of Fig. 10.24 must be designed for an equilibrium overdrive of 200 mV. If nCox = 100 A=V2 and W=L = 20=0:18, what is the required value of ISS?

38.For a MOSFET, the “current density” can be defined as the drain current divided by the device width for a given channel length. Explain how the equilibrium overdrive voltage of a MOS differential pair varies as a function of the current density.

39.A MOS differential pair contains a parasitic resistance tied between its tail node and ground (Fig. 10.72). Without using the small-signal model, prove that P is still a virtual ground for small, differential inputs.

40.In Fig. 10.25(a), Vin1 = 1:5 V and Vin2 = 0:3 V. Assuming M2 is off, determine a condition among the circuit parameters that guarantees operation of M1 in saturation.

41.Repeat Example 10.16 for a supply voltage of 2 V. Formulate the trade-off between VDD and W=L for a given output common-mode level.

42.An adventurous student constructs the circuit shown in Fig. 10.73 and calls it a “differential amplifier” because ID / (Vin1 , Vin2). Explain which aspects of our differential signals and amplifiers this circuit violates.

Figure 10.72

VDD

RD

Vout

M 1 Vin2

Vin1

Figure 10.73

43. Examine Eq. (10.134) for the following cases: (a) ID1 = 0, (b) ID1 = ISS =2, and (c) ID1 = ISS. Explain the significance of these cases.

44.Prove that the right hand side of Eq. (10.139) is always negative if the solution with the negative sign is considered.

45.From Eq. (10.142), determine the value of Vin1 , Vin2 such that ID1 , ID2 = ISS. Verify that is result is equal to p2 times the equilibrium overdrive voltage.

46.From Eq. (10.142), compute the small-signal transconductance of a MOS differential pair, defined as

Plot the result as a function of Vin1 , Vin2 and determine its maximum value.

47.Using the result obtained in Problem 46, calculate the value of Vin1 , Vin2 at which the transconductance drops by a factor of 2.

48.Suppose a new type of MOS transistor has been invented that exhibits the following I-V characteristic:

where is a proportionality factor. Figure 10.74 shows a differential pair employing such transistors.

(a)What similarities exist between this circuit and the standard MOS differential pair?

(b)Calculate the equilibrium overdrive voltage of T1 and T2.

(c)At what value of Vin1 , Vin2 does one transistor turn off?

49.Explain what happens to the characteristics shown in Fig. 10.31 if (a) the gate oxide thickness of the transistor is doubled, (b) the threshold voltage is halved, (c) ISS and W=L are halved.

50.Assuming that the mobility of carriers falls at high temperatures, explain what happens to the characteristics of Fig. 10.31 as the temperature rises.

51.A student who has a single-ended voltage source constructs the circuit shown in Fig. 10.75, hoping to obtain differential outputs. Assume perfect symmetry but = 0 for simplicity.

Figure 10.75

(a)Viewing M1 as a common-source stage degenerated by the impedance seen at the source of M2, calculate vX in terms of vin.

(b)Viewing M1 as a source follower and M2 as a common-gate stage, calculate vY in terms of vin.

(c)Add the results obtained in (a) and (b) with proper polarities. If the voltage gain is defined as (vX , vY )=vin, how does it compare with the gain of differentially-driven pairs?

52.Calculate the differential voltage gain of the circuits depicted in Fig. 10.76. Assume perfect symmetry and > 0.

Figure 10.76

53.Calculate the differential voltage gain of the circuits depicted in Fig. 10.77. Assume perfect symmetry and > 0. You may need to compute the gain as Av = ,GmRout in some cases.

Figure 10.77

54.The cascode differential pair of Fig. 10.37(a) must achieve a voltage gain of 4000. If Q1-Q4 are identical and = 100, what is the minimum required Early voltage?

55.Due to a manufacturing error, a parasitic resistance, RP , has appeared in the circuit of Fig. 10.78. Calculate the voltage gain.

I EE

Figure 10.78

56. Repeat Problem 55 for the circuit shown in Fig. 10.79.

Figure 10.79

57.Calculate the voltage gain of the degenerated pair depicted in Fig. 10.80. (Hint: Av =

,GmRout.)

R S

Figure 10.80

58.A student has mistakenly used pnp cascode transistors in a differential pair as illustrated in Fig. 10.81. Calculate the voltage gain of the circuit. (Hint: Av = ,GmRout.)

Figure 10.81

59.Realizing that the circuit of Fig. 10.81 suffers from a low gain, the student makes the modification shown in Fig. 10.82. Calculate the voltage gain of this topology.

60.The telescopic cascode of Fig. 10.38 is to operate as an op amp having an open-loop gain of 800. If Q1-Q4 are identical and so are Q5-Q8, determine the minimum allowable Early voltage. Assume n = 2 p = 100 and VA;n = 2VA;p.

61.Determine the voltage gain of the circuit depicted in Fig. 10.83. Is this topology considered a telescopic cascode?

62.The MOS cascode of Fig. 10.40(a) must provide a voltage gain of 300. If W=L = 20=0:18 for M1-M4 and nCox = 100 A=V2, determine the required tail current. Assume =

0:1 V,1.

63.The MOS telescopic cascode of Fig. 10.41(a) is designed for a voltage gain of 200 with a tail current of 1 mA. If nCox = 100 A=V2, pCox = 50 A=V2, n = 0:1 V,1, andp = 0:2 V,1, determine (W=L)1 = = (W=L)8.

64.A student adventurously modifies a CMOS telescopic cascode as shown in Fig. 10.84, where the PMOS cascode transistors are replaced with NMOS devices. Assuming > 0, compute

Figure 10.83

the voltage gain of the circuit. (Hint: the impedance seen looking into the source of M5 or M6 is not equal to 1=gmjjrO.)

65.Consider the circuit of Fig. 10.43(a) and replace REE with two parallel resistors equal to

2REE places on the two sides of the current source. Now draw a vertical line of symmetry through the circuit and decompose it to two common-mode half circuits, each having a

degeneration resistor equal to 2REE. Prove that Eq. (10.175) still holds.

66.The bipolar differential pair depicted in Fig. 10.85 must exhibit a common-mode gain of less than 0.01. Assuming VA = 1 for Q1 and Q2 but VA < 1 for Q3, prove that

67.Compute the common-mode gain of the MOS differential pair shown in Fig. 10.86. Assume= 0 for M1 and M2 but 6= 0 for M3. Prove

VbM 3

Figure 10.86

where (VGS , VT H )eq: denotes the equilibrium overdrive of M1 and M2.

68.Calculate the common-mode gain of the circuit depicted in Fig. 10.87. Assume > 0, gmrO 1, and use the relationship Av = ,GmRout.

69.Repeat Problem 68 for the circuits shown in Fig. 10.88.

70.Compute the common-mode rejection ratio of the stages illustrated in Fig. 10.89 and compare the results. For simplicity, neglect channel-length modulation in M1 and M2 but not in other transistors.

71.Determine the small-signal gain vout=i1 in the circuit of Fig. 10.90 if (W=L)3 = N(W=L)4. Neglect channel-length modulation.

VDD

Vb1 M 4

M 3

Vout

Vb2 M 5

Figure 10.87

Figure 10.88

Figure 10.89

72.In the circuit shown in Fig. 10.91, I1 changes from I0 to I0 + I and I2 from I0 to I0 , I. Neglecting channel-length modulation, calculate Vout before and after the change if

(a)(W=L)3 = (W=L)4.

(b)(W=L)3 = 2(W=L)4

73.Consider the circuit of Fig. 10.92, where the inputs are tied to a common-mode level. Assume M1 and M2 are identical and so are M3 and M4.

(a)Neglecting channel-length modulation, calculate the voltage at node N.

(b)Invoking symmetry, determine the voltage at node Y .