- •In your own words …
- •List the major components …
- •List operations …
- •Call the minimal number of levels of virtual machine..
- •D escribe the functional structure of von Neumann machine.
- •Formulate and analyze Moor’s Law.
- •Instruction
- •Interpreter
- •1 7) Describe the functional structure of Computer components …
- •22) Do we mean under the Interrupts? What is the main reason of using the Interrupt Mechanism?
- •What’s the Main Cycle of Instruction Processing (mcip)?
- •19)Describe the architecture of “Hypothetical Machine”. What is the difference between translator and interpr…
- •OpCode I Address
- •2 3) Draw up diagrams of the Program Flow Control without interrupts and with interrupts, describe each fragment of
- •25) Describe the mechanism of work with interrupts.
- •57. Describe the typical Disk data layout 29. Draw a scheme of dma Transfer
- •What is the interconnection structure, and by which factors is it determined?
- •List the types of exchanges (input and output)
- •What kind of buses does the System Bus include?
- •What do we call the width of a bus?
- •What operation does the control signal “I/o read” set?
- •What problems may arise, when only one (single) bus is used in a computer system?
- •List and describe main generic types of buses.
- •Which methods of arbitration are used now?
- •Describe existed methods of access to different types of memory.
- •Which parameters are used for the estimation memory devices performance?
- •What is ram? Describe distinguishing characteristics of ram. What’s the difference between dram…
- •48)Enumerate elements of Cache Design.
- •4 9)Draw up a block-diagram of Pentium processor and explain functions of its main nodes
- •50) How is ensured the Data Cache Consistency?
- •56. How is evaluated the Disk Access Time... Disk Access Time is the main Characteristic of Disk Performance.
- •60. Describe the process of Virtual Memory..
Which methods of arbitration are used now?
Arbitration may be centralised or distributed
Centralised
Single hardware device controlling bus access
Bus Controller
Arbiter
May be part of CPU or separate
Distributed Arbitration
Each module may claim the bus
Control logic on all modules
Describe existed methods of access to different types of memory.
Access to external devices
Sequential (The stored data and additional address information are divided into elements, called records)
Start at the current position and read through in order
Access time depends on location of data and previous location
e.g. tape
Direct
Individual blocks have unique address
Access is by jumping to vicinity(окрестность) plus sequential search
Access time depends on location and previous location
e.g. disk
In both types (direct and sequential) of accesses a combined mechanism of Read/Write is used
Access to internal devices
Random
Individual addresses identify locations exactly
Access time is independent of location or previous access
e.g. RAM
Associative
Data is located by a comparison with contents of a portion of the store
Access time is independent of location or previous access
e.g. cache
Which parameters are used for the estimation memory devices performance?
Access time
Time between presenting the address and getting the valid data (for random access).
Time, which is necessary for the transference of the Read/Write mechanism in the required position with respect to the carrier (for direct and sequential accesses).
Memory Cycle time (TC)
Time may be required for the memory to “recover” before next access
Cycle time is access + recovery
Transfer Rate (R[bit/sec])
for direct and sequential accesses: R = N/(TN – TA) ,
for random access: R= 1/ TC (inverse proportional to TC)
What is ram? Describe distinguishing characteristics of ram. What’s the difference between dram…
Memory unit is called RAM if any location can be accessed for Read or Write operation in some fixed amount of time that is independent of the location’s address
RAM
Read/Write at an arbitrary address (at random)
Volatile
Temporary storage
Static or dynamic
DRAM
Bits stored as a charge in capacitors
Charges leak
Need refreshing even when powered
Simpler construction
Smaller per bit
Less expensive
Need refresh circuits
Slower
Main memory
SRAM
Bits stored as on/off
No charges to leak
No refreshing needed when powered
More complex construction
Larger per bit
More expensive
Does not need refresh circuits
Faster
Cache
What is ROM?
Read Only Memory (ROM)
Permanent storage
Micro-programming
Library subroutines
Systems programs (BIOS)
Function table
Explain the necessity of implementation of EPROM (EEROM, Flash Memory).
Read “mostly”
Erasable Programmable (EPROM)
Erased by UV (all the storage)
Electrically Erasable (EEPROM)
Takes much longer to write than read
Flash memory (intermediate between EPROM and EEPROM)
Erase memory electrically
46) What is the main purpose of Cache Memory implementation?
Cache memory is intended to give memory speed approaching that of the fastest memories available, and at the same time provide this fast memory the price of less expensive types of semiconductor memories.
Small amount of fast memory
Sits between normal main memory and CPU (off-chip cache)
May be located on CPU chip or module (on-chip cache)
47) Describe principles of Cache Memory work.
Write Policy
Must not overwrite a cache block unless main memory is up to date
Multiple CPUs may have individual caches
I/O may address main memory directly
Write through
All writes go to main memory as well as cache
Multiple CPUs can monitor main memory traffic to keep local (to CPU) cache up to date
Lots of traffic
Slows down writes
Write back
Updates initially made in cache only
Update bit for cache slot is set when update occurs
If block is to be replaced, write to main memory only if update bit is set
Other caches get out of sync
I/O must access main memory through cache
15% of memory references are writes