mentor_instroduction

About This Manual

xi

Section 1

Overview

1-1

General VHDL Modeling Principles

1-3

Top-Down Design

1-4

Modularity

1-4

Abstraction

1-8

Information Hiding

1-9

Uniformity

1-11

Summary

1-11

Section 2

VHDL Fundamentals

2-1

VHDL Building Blocks

2-2

Major Language Constructs

2-3

Primary Language Abstraction

2-5

Design Description Methods

2-10

Structural Description

2-10

Behavioral Description

2-14

Structural and Behavioral Description Summary

2-28

Data-Flow Description

2-30

Constructs Found in Each Design Description Method

2-34

Section 3

Foundation for Declaring Objects--Types

3-1

Various Classes of Type Definitions

3-4

Scalar Types

3-4

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Section 3 Foundation for Declaring Objects--Types [continued]

Physical Types

3-4

Floating Point Types

3-6

Enumeration Types

3-7

Integer Types

3-8

Composite Types

3-9

Array Types

3-9

Record Types

3-12

File Types

3-13

Access Types

3-13

Retrieving Information on Certain Kinds of Objects

3-14

Section 4

Constructs for Decomposing Design Functionality

4-1

Concurrent Decomposition

4-3

Block Statement

4-4

Component Instantiation

4-7

Sequential Decomposition

4-12

Subprograms--Functions and Procedures

4-13

Function Call

4-24

Procedure Call

4-27

Contrasting Concurrent and Sequential Modeling

4-28

How Values Get Assigned to Signals and Variables

4-36

Resolving a Signal Value When Driven by Multiple Assignment

4-43

Statements

Creating Shared Modules--Packages

4-43

Making a Package Visible--Library Clause and Use Clause

4-48

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Mentor Graphics Introduction to VHDL, July 1994

Section 5

Global Considerations

5-1

Scope and Visibility

5-1

Reusing Predefined Names --Overloading

5-6

Overloading Enumeration Literals

5-6

Overloading Subprograms

5-7

Overloading Operators

5-11

Section 6

Coding Techniques

6-1

General VHDL Coding Guidelines

6-1

Various Techniques for Modeling Timing

6-5

Embedding Fixed-Delay Parameters Within a Model

6-6

Embedding Variable-Delay Parameters Within a Model

6-6

Using Generics to Parameterize a Model

6-8

Parameterizing Rise/Fall Delays with Generics

6-12

Increasing Model Accuracy with Error Checking

6-17

Modeling for Increased Simulation Performance

6-23

When to Use Variables Within a Loop Instead of Signals

6-23

Using Resolution Functions Only When Needed

6-25

Using Attribute ’event Instead of ’stable When Possible

6-25

Creating Lookup Tables for Logic Operations

6-27

Process Statements--Avoiding Infinite Loops

6-29

Using VHDL for Simulation Stimulus

6-32

Glossary

Glossary-1

Index

Mentor Graphics Introduction to VHDL, July 1994

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1-1. Various Things You Can Describe with VHDL

1-2

1-2.

Flat-Level Partitioning of a Hardware Design

1-5

1-3. A Hardware Module Created from VHDL Building Blocks

1-6

1-4.

Hierarchical Partioning of a VHDL Shifter Description

1-7

1-5.

Applying Abstraction to a ROM Description

1-9

1-6. Hiding Unessential Details of NAND Gate Level

1-10

2-1.

Port Clause Syntax Diagram

2-2

2-2.

Major Language Construct Hierarchy

2-4

2-3. Entity Name Usage in Entity Declaration and Architecture

Body

2-7

2-4.

Multiple Architecture Bodies for One Entity Declaration

2-9

2-5.

Symbol Representation of Two-Input Multiplexer

2-11

2-6.

A Schematic Editor Hierarchical Design of a Multiplexer

2-11

2-7.

Gate-Level Representation of Two-Input Multiplexer

2-12

2-8.

Code of Structural Description for a Multiplexer

2-12

2-9.

Two-Input Multiplexer with Associated Structural Description

2-14

2-10.

Code of Behavioral Description for a Multiplexer

2-15

2-11.

Code Example of Behavioral Description for a Shifter

2-19

2-12.

Arrays Represented as Data-Storage Containers

2-20

2-13. Variable Assignment for SHFTOUT Array After 10 ns

2-21

2-14. Variable Assignment for Array When SHFTCTL = 00

2-23

2-15. Variable Assignment for Array When SHFTCTL = 01

2-23

2-16. Variable Assignment for Array When SHFTCTL = 10

2-24

2-17. Variable Assignment for Array When SHFTCTL = 11

2-25

2-18.

Four-Bit Shifter Waveforms

2-27

2-19.

Schematic for a Four-Bit Shifter

2-27

2-20.

Comparing Structural and Behavioral Descriptions

2-29

2-21.

Example of Data-Flow Description for a Multiplexer

2-31

2-22. Comparison of Behavioral and Data-Flow Shifter

2-33

Descriptions

3-1. Various Classes of Type Definitions Within a Type

Declaration

3-3

3-2.

Defining a Constrained Array Type

3-10

3-3.

Defining a Constrained Array Matrix

3-11

3-4.

Defining an Unconstrained Array with Array Elements

3-11

3-5.

Signal Attribute Example

3-15

4-1.

Concurrent and Sequential Operations

4-2

4-2. Relating Blocks to the VHDL Hierarchy

4-5

4-3.

Using the Guard Expression on a Bistable Latch

4-6

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Mentor Graphics Introduction to VHDL, July 1994

4-4. Instantiating an AND Gate in a MUX Description

4-10

4-5.

Instantiating a Component Using Different Parameters

4-11

4-6.

Using Procedures and Functions

4-16

4-7. Code Example of a Subprogram--RAM Load Procedure

4-17

4-8. Code Example of a Subprogram--RAM Read Procedure

4-20

4-9. Example of a Subprogram--Concatenate Data Procedure

4-22

4-10. Code Example of a Subprogram--Parity Checker Function

4-23

4-11.

Associating Actual Parameters to Formal Parameters

4-25

4-12.

Positional Parameter Notation in a Function Call

4-26

4-13.

Procedure Call Parameter Association

4-28

4-14.

Evaluation Flow for First Behavioral AOI Models

4-32

4-15.

AND/OR/Inverter Circuit

4-34

4-16.

Operation-Flow Diagram for AOI Circuit

4-35

4-17. Changing Model Behavior by Moving Sequential Statements

4-38

4-18. Shared Module of Code Defined as a Package

4-44

4-19.

Portion of Code from a Package Called Standard

4-45

4-20. Effects on Entity and Architecture When Changing Package

Header

4-47

4-21.

Making Packages Visible with Library and Use Clauses

4-49

4-22. Coupling Two Procedures to One Package with Use Clauses

4-51

5-1.

Example of Scope and Visibility

5-3

5-2. Hiding a Declaration Using a Homograph

5-5

5-3.

Overloading Enumeration Literals

5-7

5-4.

Overloading Subprograms--Functions

5-9

5-5.

Calling a Specific Overloaded Subprogram--Function

5-10

5-6.

Overloading Operators

5-12

5-7.

Calling a Specific Overloaded Operator

5-13

6-1.

Good Presentation Style for Shifter Description

6-4

6-2.

Poor Presentation Style for Shifter Description

6-5

6-3. Embedding Variable-Delay Parameters Within Model

6-7

6-4. Test Bed Code for AND Gate Model

6-8

6-5. AND Gate Model Using Generics to Receive Timing

Parameters

6-10

6-6.

Using Generics to Pass Customized Parameters to a Model

6-11

6-7. Entity for One-Bit Latch Using Parameterized Rise/Fall

Delays

6-13

6-8.

Rise/Fall Values Passed to One-Bit Latch Model

6-14

6-9. Test Bed Code for Latch Model

6-15

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6-10. Architecture Body for One-Bit Latch with Parameterized

6-16

Delays

6-11.

Error-Checking Code Added to Entity for One-Bit Latch

6-18

6-12.

Comparing a Signal with Its Delayed Counterpart

6-20

6-13.

Setup/Hold Timing for Latch

6-22

6-14. Signal Assignment Within a Loop

6-24

6-15. Logic Example Package

6-28

6-16.

Correcting an Infinite Loop in a Process Statement

6-30

6-17.

Wait Statement in a Procedure Avoids an Infinite Loop

6-31

6-18. VHDL Model Used as Stimulus for AND Gate

6-33

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Mentor Graphics Introduction to VHDL, July 1994

4-1.

AND/OR/INVERT Truth Table

4-29

4-2.

AND/OR/Invert Karnaugh Map

4-30

5-1.

Operators by Precedence

5-11

6-1.

Constant Values Set in Latch Test Bed Model

6-17

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Mentor Graphics Introduction to VHDL, July 1994