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Аналіз обчислювальної похибки при виконанні базових операцій алгоритмів цифрової обробки сигналів. Обчислення математичних функцій роектування комп’ютерних засобів обробки сигналів та зображень Ваврук. Лаби для 13 групи / MAZ / MAZ-DOD-MAT-2012 / tms320tci6616.pdf

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INFORMATION ADVANCE

TMS320TCI6616
Communications Infrastructure KeyStone SoC
SPRS624A—January 2011				www.ti.com
				www.ti.com
Table 7-23	Device Master Settings (Part 2 of 2)

Privilege ID	Master	Privilege Level	Security Level	Access Type
9	SRIO_CPPI/SRIO_M	User/Driven by SRIO block, User mode and supervisor mode is determined	Non-secure	DMA
		by per transaction basis. Only the transaction with source ID matching the
		value in SupervisorID register is granted supervisor mode.

10	QM_CDMA/QM_second	User	Non-secure	DMA

11	PCIe	Supervisor	Non-secure	DMA

12	DAP	Driven by debug_SS	Driven by	DMA
			debug_SS

13	Reserved	Supervisor	Non-secure	DMA

14	Reserved	Supervisor	Non-secure	DMA

15	Reserved	User	Non-secure	DMA

End of Table 7-23

7.6.1 MPU Registers

This section includes the offsets for MPU registers and definitions for device specific MPU registers.

7.6.1.1 MPU Register Map

Table 7-24	MPU0 Registers (Part 1 of 2)

Offset	Name	Description
0h	REVID	Revision ID

4h	CONFIG	Configuration

10h	IRAWSTAT	Interrupt raw status/set

14h	IENSTAT	Interrupt enable status/clear

18h	IENSET	Interrupt enable

1Ch	IENCLR	Interrupt enable clear

20h	EOI	End of interrupt

200h	PROG1_MPSAR	Programmable range 1, start address

204h	PROG1_MPEAR	Programmable range 1, end address

208h	PROG1_MPPA	Programmable range 1, memory page protection attributes

210h	PROG2_MPSAR	Programmable range 2, start address

214h	PROG2_MPEAR	Programmable range 2, end address

218h	PROG2_MPPA	Programmable range 2, memory page protection attributes

220h	PROG3_MPSAR	Programmable range 3, start address

224h	PROG3_MPEAR	Programmable range 3, end address

228h	PROG3_MPPA	Programmable range 3, memory page protection attributes

230h	PROG4_MPSAR	Programmable range 4, start address

234h	PROG4_MPEAR	Programmable range 4, end address

238h	PROG4_MPPA	Programmable range 4, memory page protection attributes

240h	PROG5_MPSAR	Programmable range 5, start address

244h	PROG5_MPEAR	Programmable range 5, end address

248h	PROG5_MPPA	Programmable range 5, memory page protection attributes

250h	PROG6_MPSAR	Programmable range 6, start address

254h	PROG6_MPEAR	Programmable range 6, end address

258h	PROG6_MPPA	Programmable range 6, memory page protection attributes

260h	PROG7_MPSAR	Programmable range 7, start address


134		Copyright 2011 Texas Instruments Incorporated

		TMS320TCI6616
		Communications Infrastructure KeyStone SoC
www.ti.com		SPRS624A—January 2011
www.ti.com
Table 7-24	MPU0 Registers (Part 2 of 2)

Offset	Name	Description
264h	PROG7_MPEAR	Programmable range 7, end address

268h	PROG7_MPPA	Programmable range 7, memory page protection attributes

270h	PROG8_MPSAR	Programmable range 8, start address

274h	PROG8_MPEAR	Programmable range 8, end address

278h	PROG8_MPPA	Programmable range 8, memory page protection attributes

280h	PROG9_MPSAR	Programmable range 9, start address

284h	PROG9_MPEAR	Programmable range 9, end address

288h	PROG9_MPPA	Programmable range 9, memory page protection attributes

290h	PROG10_MPSAR	Programmable range 10, start address

294h	PROG10_MPEAR	Programmable range 10, end address

298h	PROG10_MPPA	Programmable range 10, memory page protection attributes

2A0h	PROG11_MPSAR	Programmable range 11, start address

2A4h	PROG11_MPEAR	Programmable range 11, end address

2A8h	PROG11_MPPA	Programmable range 11, memory page protection attributes

2B0h	PROG12_MPSAR	Programmable range 12, start address

2B4h	PROG12_MPEAR	Programmable range 12, end address

2B8h	PROG12_MPPA	Programmable range 12, memory page protection attributes

2C0h	PROG13_MPSAR	Programmable range 13, start address

2C4h	PROG13_MPEAR	Programmable range 13, end address

2C8h	PROG13_MPPA	Programmable range 13, memory page protection attributes

2D0h	PROG14_MPSAR	Programmable range 14, start address

2D4h	PROG14_MPEAR	Programmable range 14, end address

2Dh	PROG14_MPPA	Programmable range 14, memory page protection attributes

2E0h	PROG15_MPSAR	Programmable range 15, start address

2E4h	PROG15_MPEAR	Programmable range 15, end address

2E8h	PROG15_MPPA	Programmable range 15, memory page protection attributes

2F0h	PROG16_MPSAR	Programmable range 16, start address

2F4h	PROG16_MPEAR	Programmable range 16, end address

2F8h	PROG16_MPPA	Programmable range 16, memory page protection attributes

300h	FLTADDRR	Fault address

304h	FLTSTAT	Fault status

308h	FLTCLR	Fault clear

End of Table 7-24

Table 7-25	MPU1 Registers (Part 1 of 2)

Offset	Name	Description
0h	REVID	Revision ID

4h	CONFIG	Configuration

10h	IRAWSTAT	Interrupt raw status/set

14h	IENSTAT	Interrupt enable status/clear

18h	IENSET	Interrupt enable

1Ch	IENCLR	Interrupt enable clear

20h	EOI	End of interrupt


Copyright 2011 Texas Instruments Incorporated		135

ADVANCE INFORMATION

INFORMATION ADVANCE

TMS320TCI6616
Communications Infrastructure KeyStone SoC
SPRS624A—January 2011		www.ti.com
		www.ti.com
Table 7-25	MPU1 Registers (Part 2 of 2)

Offset	Name	Description
200h	PROG1_MPSAR	Programmable range 1, start address

204h	PROG1_MPEAR	Programmable range 1, end address

208h	PROG1_MPPA	Programmable range 1, memory page protection attributes

210h	PROG2_MPSAR	Programmable range 2, start address

214h	PROG2_MPEAR	Programmable range 2, end address

218h	PROG2_MPPA	Programmable range 2, memory page protection attributes

220h	PROG3_MPSAR	Programmable range 3, start address

224h	PROG3_MPEAR	Programmable range 3, end address

228h	PROG3_MPPA	Programmable range 3, memory page protection attributes

230h	PROG4_MPSAR	Programmable range 4, start address

234h	PROG4_MPEA	Programmable range 4, end address

238h	PROG4_MPPA	Programmable range 4, memory page protection attributes

300h	FLTADDRR	Fault address

304h	FLTSTAT	Fault status

308h	FLTCLR	Fault clear

End of Table 7-25

Table 7-26	MPU2 Registers (Part 1 of 2)

Offset	Name	Description
0h	REVID	Revision ID

4h	CONFIG	Configuration

10h	IRAWSTAT	Interrupt raw status/set

14h	IENSTAT	Interrupt enable status/clear

18h	IENSET	Interrupt enable

1Ch	IENCLR	Interrupt enable clear

20h	EOI	End of interrupt

200h	PROG1_MPSAR	Programmable range 1, start address

204h	PROG1_MPEAR	Programmable range 1, end address

208h	PROG1_MPPA	Programmable range 1, memory page protection attributes

210h	PROG2_MPSAR	Programmable range 2, start address

214h	PROG2_MPEAR	Programmable range 2, end address

218h	PROG2_MPPA	Programmable range 2, memory page protection attributes

220h	PROG3_MPSAR	Programmable range 3, start address

224h	PROG3_MPEAR	Programmable range 3, end address

228h	PROG3_MPPA	Programmable range 3, memory page protection attributes

230h	PROG4_MPSAR	Programmable range 4, start address

234h	PROG4_MPEAR	Programmable range 4, end address

238h	PROG4_MPPA	Programmable range 4, memory page protection attributes

240h	PROG5_MPSAR	Programmable range 5, start address

244h	PROG5_MPEAR	Programmable range 5, end address

248h	PROG5_MPPA	Programmable range 5, memory page protection attributes

250h	PROG6_MPSAR	Programmable range 6, start address

254h	PROG6_MPEAR	Programmable range 6, end address


136		Copyright 2011 Texas Instruments Incorporated

		TMS320TCI6616
		Communications Infrastructure KeyStone SoC
www.ti.com		SPRS624A—January 2011
www.ti.com
Table 7-26	MPU2 Registers (Part 2 of 2)

Offset	Name	Description
258h	PROG6_MPPA	Programmable range 6, memory page protection attributes

260h	PROG7_MPSAR	Programmable range 7, start address

264h	PROG7_MPEAR	Programmable range 7, end address

268h	PROG7_MPPA	Programmable range 7, memory page protection attributes

270h	PROG8_MPSAR	Programmable range 8, start address

274h	PROG8_MPEAR	Programmable range 8, end address

278h	PROG8_MPPA	Programmable range 8, memory page protection attributes

280h	PROG9_MPSAR	Programmable range 9, start address	INFORMATION

284h	PROG9_MPEAR	Programmable range 9, end address
284h	PROG9_MPEAR	Programmable range 9, end address

288h	PROG9_MPPA	Programmable range 9, memory page protection attributes

290h	PROG10_MPSAR	Programmable range 10, start address

294h	PROG10_MPEAR	Programmable range 10, end address

298h	PROG10_MPPA	Programmable range 10, memory page protection attributes

2A0h	PROG11_MPSAR	Programmable range 11, start address

2A4h	PROG11_MPEAR	Programmable range 11, end address

2A8h	PROG11_MPPA	Programmable range 11, memory page protection attributes

2B0h	PROG12_MPSAR	Programmable range 12, start address
			ADVANCE
2B4h	PROG12_MPEAR	Programmable range 12, end address

2D4h	PROG14_MPEAR	Programmable range 14, end address
2B8h	PROG12_MPPA	Programmable range 12, memory page protection attributes
2C0h	PROG13_MPSAR	Programmable range 13, start address
2C4h	PROG13_MPEAR	Programmable range 13, end address
2C8h	PROG13_MPPA	Programmable range 13, memory page protection attributes

2D0h	PROG14_MPSAR	Programmable range 14, start address


2Dh	PROG14_MPPA	Programmable range 14, memory page protection attributes

2E0h	PROG15_MPSAR	Programmable range 15, start address

2E4h	PROG15_MPEAR	Programmable range 15, end address

2E8h	PROG15_MPPA	Programmable range 15, memory page protection attributes

2F0h	PROG16_MPSAR	Programmable range 16, start address

2F4h	PROG16_MPEAR	Programmable range 16, end address

2F8h	PROG16_MPPA	Programmable range 16, memory page protection attributes

300h	FLTADDRR	Fault address

304h	FLTSTAT	Fault status

308h	FLTCLR	Fault clear

End of Table 7-26

Table 7-27	MPU3 Registers (Part 1 of 2)

Offset	Name	Description
0h	REVID	Revision ID

4h	CONFIG	Configuration

10h	IRAWSTAT	Interrupt raw status/set

14h	IENSTAT	Interrupt enable status/clear

18h	IENSET	Interrupt enable


Copyright 2011 Texas Instruments Incorporated		137

INFORMATION ADVANCE

TMS320TCI6616
Communications Infrastructure KeyStone SoC
SPRS624A—January 2011		www.ti.com
		www.ti.com
Table 7-27	MPU3 Registers (Part 2 of 2)

Offset	Name	Description
1Ch	IENCLR	Interrupt enable clear

20h	EOI	End of interrupt

200h	PROG1_MPSAR	Programmable range 1, start address

204h	PROG1_MPEAR	Programmable range 1, end address

208h	PROG1_MPPA	Programmable range 1, memory page protection attributes

300h	FLTADDRR	Fault address

304h	FLTSTAT	Fault status

308h	FLTCLR	Fault clear

End of Table 7-27

Table 7-28	MPU4 Registers

Offset	Name	Description
0h	REVID	Revision ID

4h	CONFIG	Configuration

10h	IRAWSTAT	Interrupt raw status/set

14h	IENSTAT	Interrupt enable status/clear

18h	IENSET	Interrupt enable

1Ch	IENCLR	Interrupt enable clear

20h	EOI	End of interrupt

200h	PROG1_MPSAR	Programmable range 1, start address

204h	PROG1_MPEAR	Programmable range 1, end address

208h	PROG1_MPPA	Programmable range 1, memory page protection attributes

210h	PROG2_MPSAR	Programmable range 2, start address

214h	PROG2_MPEAR	Programmable range 2, end address

218h	PROG2_MPPA	Programmable range 2, memory page protection attributes

300h	FLTADDRR	Fault address

304h	FLTSTAT	Fault status

308h	FLTCLR	Fault clear

End of Table 7-28

138	Copyright 2011 Texas Instruments Incorporated

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