Добавил:

Upload Опубликованный материал нарушает ваши авторские права? Сообщите нам.

Вуз:

Национальный университет Львовская политехника

Предмет:

[НЕСОРТИРОВАННОЕ]

Файл:

tms320c17

.pdf

Скачиваний:

Добавлен:

12.02.2016

Размер:

936.25 Кб

Скачать

☆

<<< < Предыдущая 1 2 3 4 5 6 78 / 148 9 10 11 12 13 14 > Следующая >>>

TMS320LC15

DIGITAL SIGNAL PROCESSOR

SPRS009C ± JANUARY 1987 ± REVISED JULY 1991

CLOCK CHARACTERISTICS AND TIMING

The ′LC15 can use either its internal oscillator or an external frequency source for a clock.

internal clock option

The internal oscillator is enabled by connecting a crystal across X1 and X2/CLKIN (see Figure 1). The frequency of CLKOUT is one-fourth the crystal fundamental frequency. The crystal should be fundamental mode, and parallel resonant, with an effective series resistance of 30 ohms, a power dissipation of 1 mW, and be specified at a load capacitance of 20 pF.

PARAMETER	TEST CONDITIONS	MIN	NOM	MAX	UNIT

Crystal frequency fx	TA = ± 40°C to 85°C	4.0		16	MHz
C1, C2	TA = ± 40°C to 85°C		10		pF
C1, C2			10		pF

external clock option

An external frequency source can be used by injecting the frequency directly into X2/CLKIN with X1 left unconnected. The external frequency injected must conform to the specifications listed in the table below.

switching characteristics over recommended operating conditions

	PARAMETER	TEST CONDITIONS			MIN	NOM	MAX	UNIT

t	CLKOUT cycle time²				250		1000	ns
c(C)
t	CLKOUT rise time	R	L	= 825 Ω,		10³		ns
r(C)			L
tf(C)	CLKOUT fall time	CL = 100 pF,				8³		ns
t	Pulse duration, CLKOUT low	(see Figure 2)				117³		ns
w(CL)
tw(CH)	Pulse duration, CLKOUT high					115³		ns
td(MCC)	Delay time, CLKIN↑ to CLKOUT↓				20		70	ns

timing requirements over recommended operating conditions

		MIN	NOM	MAX	UNIT

tc(MC)	Master clock cycle time	62.5		150	ns
tr(MC)	Rise time, master clock input		5³	10²	ns
tf(MC)	Fall time, master clock input		5³	10²	ns
tw(MCP)	Pulse duration, master clock	0.4t c(MC)³	0.6t c(MC)³		ns
tw(MCL)	Pulse duration, master clock low at tc(MC) min		26		ns
tw(MCH)	Pulse duration, master clock high at tc(MC) min		26		ns

² tc(C) is the cycle time of CLKOUT, i.e., 4tc(MC) (4 times CLKIN cycle time if an external oscillator is used) ³ Values derived from characterization data and not tested.

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001

TMS320LC15

DIGITAL SIGNAL PROCESSOR

SPRS009C± JANUARY 1987 ± REVISED JULY 1991

electrical characteristics over specified temperature range (unless otherwise noted)

PARAMETER		TEST CONDITIONS			MIN	TYP²	MAX	UNIT
ICC³		f = 16.0 MHz, VCC = 3.6 V, TA = 0°C to 70°C				15	20	mA
² All typical values are at T	= 70°C and are used for thermal resistance calculations.
A
³ I characteristics are inversely proportional to temperature. For I			CC	dependence on frequency, see figure below.
CC			CC

typical power vs. frequency graph (outputs unloaded)§
	20.0
	15.0
(mA)	10.0
CC	10.0
CC
I
	5.0
	0.0						12	14	16
	0	2	4	6	8	10	12	14	16
				CLKIN Frequency, MHz
				± 40 °C to 85°C Temperature Range

VCC = 3.5 V

VCC = 3 V

§Device operation is not guaranteed below 4 MHz CLKIN. Graph is for device in RESET; i.e., only clock-out is driven.

72	POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001

TMS320LC15

DIGITAL SIGNAL PROCESSOR

SPRS009C ± JANUARY 1987 ± REVISED JULY 1991

MEMORY AND PERIPHERAL INTERFACE TIMING

switching characteristics over recommended operating conditions

PARAMETER

TEST CONDITIONS

MIN

MAX

UNIT

Delay time CLKOUT↓ to address bus valid

10²

Delay time CLKOUT↓ to

↓

1/4 t

±5²

1/4 t

+25

MEN

c(C)

Delay time CLKOUT↓ to

↑

±10²

MEN

Delay time CLKOUT↓ to

↓

1/4 t

±5²

1/4 t

+25

DEN

c(C)

td5

Delay time CLKOUT↓ to

↑

±10²

DEN

td6

Delay time CLKOUT↓ to

↓

1/2 tc(C)±5²

1/2 tc(C)+25

RL = 825Ω,

CL = 100 pF,

Delay time CLKOUT↓ to WE↑

±10

(see Figure 2)

td8

Delay time CLKOUT↓ to data bus OUT valid

1/4 tc(C)+75

Time after CLKOUT↓ that data bus starts to be driven

1/4 t

±5²

c(C)

td10

Time after CLKOUT↓ that data bus stops being driven

1/4 tc(C)+60

Data bus OUT valid after CLKOUT↓

1/4 tc(C)±10

Address hold time after WE↑,

↑, or

↑ (see Note 14)

0²

MEN

DEN

h(A-WMD)

Address bus setup time to

↓

± 4²

DEN

su(A-MD)

² Values derived from characterization data and not tested. NOTE 14: Address bus will be valid upon WE↑, MEN↑, or DEN↑.

timing requirements over recommended operating conditions

		TEST CONDITIONS	MIN	NOM	MAX	UNIT

t	Setup time data bus valid prior to CLKOUT↓	RL = 825Ω,	56			ns
su(D)		CL = 100 pF,
th(D)	Hold time, data bus held valid after CLKOUT↓ (see Note 9)	CL = 100 pF,	0			ns
th(D)	Hold time, data bus held valid after CLKOUT↓ (see Note 9)	(see Figure 2)	0			ns

NOTE 9: Data may be removed from the data bus upon MEN↑ or DEN↑ preceding CLKOUT↓.

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001

TMS320LC15

DIGITAL SIGNAL PROCESSOR

SPRS009C± JANUARY 1987 ± REVISED JULY 1991

RESET (RS) TIMING

switching characteristics over recommended operating conditions

TEST CONDITIONS

MIN

NOM

MAX

UNIT

Delay time,

↑,

↑, and

↑ from

RL = 825Ω,

1/2t

+75

DEN

MEN

c(C)

d11

CL = 100 pF,

tdis(R)

Data bus disable time after RS

1/4tc(C)+75

(see Figure 2)

² These parameters do not apply to this device.

timing requirements over recommended operating conditions

							MIN	NOM	MAX	UNIT

tsu(R)	Reset					setup time prior to CLKOUT (see Note 10)	85			ns
tsu(R)	Reset				(RS)	setup time prior to CLKOUT (see Note 10)	85			ns
tw(R)			pulse duration				5tc(C)			ns
tw(R)	RS		pulse duration				5tc(C)			ns
NOTE 10:
NOTE 10:		RS		can occur anytime during a clock cycle. Time given is minimum to ensure synchronous operation.

INTERRUPT (INT) TIMING

timing requirements over recommended operating conditions

						MIN	NOM	MAX	UNIT

tF(INT)	Fall time,							15	ns
tF(INT)	Fall time,	INT						15	ns
tw(INT)	Pulse duration,					tc(C)			ns
tw(INT)	Pulse duration,			INT		tc(C)			ns
tsu(INT)	Setup time,				↓ before CLKOUT↓	85			ns
tsu(INT)	Setup time,		INT		↓ before CLKOUT↓	85			ns

I/O (BIO) TIMING

timing requirements over recommended operating conditions

						MIN	NOM	MAX	UNIT

tf(IO)	Fall time							15	ns
tf(IO)	Fall time	BIO						15	ns
tw(IO)	Pulse duration					tc(C)			ns
tw(IO)	Pulse duration			BIO		tc(C)			ns
tsu(IO)	Setup time				↓ before CLKOUT↓	85			ns
tsu(IO)	Setup time		BIO		↓ before CLKOUT↓	85			ns

74	POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001

TMS320LC15

DIGITAL SIGNAL PROCESSOR

SPRS009C ± JANUARY 1987 ± REVISED JULY 1991

clock timing

tr(MC)	tw(MCH)	tw(MCP)²
tc(MC)		tw(MCP)²
tc(MC)
X2/CLKIN
tw(MCL)
tf(MC)		tw(CH)
td(MCC)²		tw(CH)
td(MCC)²
CLKOUT
tf(C)		tr(C)

tw(CL)

tc(C)

² td(MCC) and tw(MCP) are referenced to an intermediate level of 1.5 V on the CLKIN waveform.

IN instruction timing

CLKOUT

	MEN		1		2
			1	tsu(A-MD)	2
				tsu(A-MD)	tsu(D)
					tsu(D)
	PA2-PA0		3	4	5
			td4		td5
	DEN
					th(D)
	D15-D0		6	7	8
Legend:
1.	IN Instruction Prefetch	5.	Address Bus Valid
2.	Next Instruction Prefetch	6.	Instruction Valid
3.	Address Bus Valid	7.	Data Input Valid
4.	Peripheral Address Valid	8.	Instruction Valid

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001

TMS320LC15

DIGITAL SIGNAL PROCESSOR

SPRS009C± JANUARY 1987 ± REVISED JULY 1991

OUT instruction timing

CLKOUT

	MEN		1		2
	PA2-PA0		3	4	5
			td6	td7
	WE		td9	td10
			td8	td10
			td8	tv
	D15-D0		6	7	8
Legend:
1.	OUT Instruction Prefetch	5.	Address Bus Valid
2.	Next Instruction Prefetch	6.	Instruction Valid
3.	Address Bus Valid	7.	Data Output Valid
4.	Peripheral Address Valid	8.	Instruction Valid
external memory read timing
			tc(C)
	CLKOUT
	td3		td2
	td3
	MEN
			tsu(A-MD)		th(A-WMD)
			td1		th(A-WMD)
	A11-A0			Address Bus Valid
				tsu(D)	th(D)
					th(D)
	D15-D0			Instruction Valid

76	POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001

TMS320LC15

DIGITAL SIGNAL PROCESSOR

SPRS009C ± JANUARY 1987 ± REVISED JULY 1991

TBLR instruction timing

	CLKOUT
				td3	td2		td3
	MEN		1	2	3		4
			1	2	3		4
					td1
	A11-A0		5	6	7		8
					tsu(D)		th(D)
					tsu(D)
	D15-D0		9	10	11		12
Legend:
1.	TBLR Instruction Prefetch	7.	Address Bus Valid
2.	Dummy Prefetch	8.	Address Bus Valid
3.	Data Fetch	9.	Instruction Valid
4.	Next Instruction Prefetch	10.	Instruction Valid
5.	Address Bus Valid	11.	Data Input Valid
6.	Address Bus Valid	12.	Instruction Valid
TBLW instruction timing
	CLKOUT
	MEN		1		2		3
			1		2		3
	A11-A0		4		5	6	7
					td6		td7
	WE						td10
					td8		td10
					td9		tv
	D15-D0		8		9	10	11
Legend:
1.	TBLW Instruction Prefetch	7.	Address Bus Valid
2.	Dummy Prefetch	8.	Instruction Valid
3.	Next Instruction Prefetch	9.	Instruction Valid
4.	Address Bus Valid	10.	Data Output Valid
5.	Address Bus Valid	11.	Instruction Valid
6.	Address Bus Valid

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001

TMS320LC15

DIGITAL SIGNAL PROCESSOR

SPRS009C± JANUARY 1987 ± REVISED JULY 1991

reset timing

CLKOUT
		tsu(R)	tsu(R)
RS
		tw(R)
DEN
WE (see			Data In From	Data In From
MEN Note E)		td11	PC ADDR 0	PC ADDR PC+1
	tdis(R)	Data Shown Relative To WE
D15-D0		Data Shown Relative To WE
D15-D0
MEN
	AB = Address Bus			AB = PC+1
ADDRESS	AB = PC	AB = PC+1	AB = PC = 0
BUS	AB = PC	AB = PC+1	AB = PC = 0
BUS

NOTES: A. RS forces DEN, WE, and MEN high and places data bus D0 through D15 in a high-impedance state. AB outputs (and program count- er) are synchronously cleared to zero after the next complete CLK cycle from RS↓.

B.RS must be maintained for a minimum of five clock cycles.

C.Resumption of normal program will commence after one complete CLK cycle from RS↑.

D.Due to the synchronization action on RS, time to execute the function can vary dependent upon when RS↑ or RS↓occur in the CLK cycle.

E.Diagram shown is for definition purpose only. DEN, WE, and MEN are mutually exclusive.

F.During a write cycle, RS may produce an invalid write address.

interrupt timing

CLKOUT

tsu(INT)

INT

tf(INT)

tw(INT)

BIO timing

CLKOUT

tsu(IO)

BIO

tf(IO)

tw(IO)

78	POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001

TMS320C16 DIGITAL SIGNAL PROCESSOR

SPRS009C ± JANUARY 1987 ± REVISED JULY 1991

Key Features: TMS320C16

•114-ns Instruction Cycle Time

•256 Words of On-Chip Data RAM

•8K Words of On-Chip Program ROM

•64K Words Total External Memory at Full Speed

•8 Level Stack

•32-Bit ALU/Accumulator

•16 × 16-Bit Multiplier With 32-Bit Product

•16-Bit Barrel Shifter

•Eight Input and Eight Output Channels

•Simple Memory and I/O Interface:

ÐMemory Write Enable Signal MWE

ÐI/O Write Enable Signal IOWE

•Single 5-V Supply

•64-Pin Quad Flatpack (PG Suffix)

•Operating Free-Air Temperature Range

. . . 0°C to 70°C

+5 V

GND

	Interrupt	256-Word RAM
	Interrupt	Data (16)
		Data (16)
		8K-Word ROM

32-Bit ALU/ACC

8-Level Stack

Multiplier

Address (12)

Shifters

PG Package

(Top View)

			BIO INT	MC/MP	V V V V V			MEN NC	IOEN	MWE	IOWE
						SS DD DD DD DD





	64 63 62 61 60 59 58 57 56 55 54 53 52
NC		1					51					NC
NC		1					51					NC
RS		2					50					NC
RS		2					50					NC
X1		3					49					A0/PA0
X1		3					49					A0/PA0
X2/CLKIN		4					48					A1/PA1
X2/CLKIN		4					48					A1/PA1
VSS		5					47					A2/PA2
		5					47

VSS		6					46					A3
VSS												A3
VSS		7					45					A4
VSS												A4
VSS		8					44					A5
VSS												A5
CLKOUT		9					43					A6
D15		10					42					VSS
		10					42

D14		11					41					A7
NC		12					40					A8
NC		12					40					A8
D13		13					39					A9
D13		13					39					A9
D12		14					38					A10
D12		14					38					A10
D11		15					37					A11
D11		15					37					A11
D10		16					36					A12
D10		16					36					A12
D9		17					35					A13
D9		17					35					A13
NC		18					34					A14
NC		18					34					A14
NC		19					33					NC
NC		19					33					NC
	20 21 22 23 24 25 26 27 28 29 30 31 32

D8 D7 D6 D5 NC	V	D3 D2 NC D1 D0 A15
	D4 DD

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001

TMS320C16

DIGITAL SIGNAL PROCESSOR

SPRS009C± JANUARY 1987 ± REVISED JULY 1991

			TERMINAL FUNCTIONS

PIN		I/O/Z²	DESCRIPTION
NAME	NO.		ADDRESS/DATA BUSES

A15 MSB	32	I/O/Z	Program memory address bus A15 (MSB) through A0 (LSB) and port addresses PA2 (MSB) through
A14	34		PA0 (LSB). Addresses A15 through A0 are always active and never go to high impedance. During
A14	34		execution of the IN and OUT instructions, pins A2 through A0 carry the port addresses. (Address pins
A13	35
A13	35		A15 through A3 are always driven low on IN and OUT instruction.
A12	36
A12	36
A11	37
A10	38
A9	39
A8	40
A7	41
A6	43
A5	44
A4	45
A3	46
A2/PA2	47
A1/PA1	48
A0/PA0	49

D15 MSB	10	I/O/Z	Parallel data bus D15 (MSB) through D0 (LSB). The data bus is always in the high-impedance state
D14	11		except when IOWE or MWE are active (low).
D13	13
D12	14
D11	15
D10	16
D9	17
D8	20
D7	21
D6	22
D5	23
D4	25
D3	27
D2	28
D1	30
D0 LSB	31

² Input/Output/High-impedance state.

80	POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001

<<< < Предыдущая 1 2 3 4 5 6 78 / 148 9 10 11 12 13 14 > Следующая >>>

Соседние файлы в папке MAZ-DOD-MAT-2012

#
12.02.2016715.41 Кб41ADSP-BF535_a.pdf
#
12.02.20162.44 Mб39ADSP-TS101S_0.pdf
#
12.02.20161.75 Mб46ADSP-TS201S.pdf
#
12.02.2016284.83 Кб39ADSP21msp58.pdf
#
12.02.2016396.58 Кб39Efficient Floating-Point FFTs for ADSP-TS201 TigerSHARC Processors.pdf
#
12.02.2016936.25 Кб41tms320c17.pdf
#
12.02.2016562.87 Кб39tms320c25.pdf
#
12.02.2016792.32 Кб38tms320c30.pdf
#
12.02.2016710.55 Кб41tms320c40.pdf
#
12.02.20161.25 Mб42tms320c50.pdf
#
12.02.20161.51 Mб39TMS320C6203.pdf