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TMS320E14, TMS320P14

DIGITAL SIGNAL PROCESSORS

				SPRS009C ± JANUARY 1987 ± REVISED JULY 1991
program cycle timing
	Program		Verify
	Program
A12-A0		Address Stable		VIH
A12-A0		Address Stable		Address N+1
	tsu(A)			VIL
	tsu(A)			th(A)
			Data Out	VIH/VOH
Q8-Q1	Data In Stable	HI-Z	Data Out
Q8-Q1	Data In Stable	HI-Z	Valid	VIL/VOL
				VIL/VOL
	tsu(D)			tdis(G)²
VPP				VPP
VPP	tsu(VPP)
	tsu(VPP)			VCC
VCC				VCCP
VCC	tsu(VCC)
	tsu(VCC)			VCC
E				VIH
E
	tsu(E)	th(D)		VIL
	tsu(E)	th(D)		VIH
				VIH
PGM			ten(G)²	VIL
			ten(G)²	VIL
	tw(FPGM)		tsu(G)

VIH

VIL

² tdis(G) and ten(G) are characteristics of the device but must be accommodated by the programmer.

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001

TMS320C15, TMS320E15, TMS320LC15, TMS320P15

DIGITAL SIGNAL PROCESSORS

SPRS009C± JANUARY 1987 ± REVISED JULY 1991

Key Features: TM320C15/E15/LC15/P15

+5 V

• Instruction Cycle Timing:

+3.3 V

GND

160-ns (TMS320C15-25/E15-25)

200-ns (TMS320C15/E15/P15)

250-ns (TMS320LC15)

• 256 Words of On-Chip Data RAM

Interrupt

256-Word RAM

• 4K Words of On-Chip Program ROM

Data (16)

4K-Word ROM/EPROM

(TMS320C15/C15-25/LC15)

• 4K Words of On-Chip Program EPROM

32-Bit ALU/ACC

(TMS320E15/E15-25)

• One-Time Programmable (OTP) Windowless

Multiplier

Address (12)

EPROM Version Available (TMS320P15)

Shifters

• EPROM Code Protection for Copyright Security

• External Memory up to 4K-Words at Full Speed

• 16 × 16-Bit Multiplier With 32-Bit Product

• 0 to 16-Bit Barrel Shifter

• On-Chip Clock Oscillator

• 3.3-V Low-Power Version Available (TMS320LC15)

• Device Packaging:

Ð 40-Pin Dip (All Devices)

44-Lead PLCC (TMS320C15/C15-25/LC15/P15)

44-Lead-QUAD (TMS320E15/E15-25)

TMS320C15/E15/LC15/P15

N/JD Package

FN/FZ Package

(Top View)

INT RS

MC/MP A0/PA0 A1/PA1 V A2/PA2 A3 A4 A5 A6

A1/PA1

A2/PA2

A0/PA0

MC/MP

1 44 43 42 41 40

INT

CLKOUT

X2/CLKIN

MEN

X2/CLKIN

MEN

BIO

DEN

BIO

DEN

VSS

VCC

A10

D10

A10

D10

A11

D11

A11

D11

D12

D13

18 19 20 21 22 23 24 25 26 27 28

D14

D13

D14

D15

D6 D5 D4 D3 D2 V

D15

52	POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001

functional block diagram

		X1
	CLKOUT	X2/CLKIN
WE		16
DEN		16
DEN		Controller
MEN		Controller
MEN
BIO
MC/MP
INT
RS
A11-A0/	MUX	3
A11-A0/
PA2-PA0
		3

TMS320C15, TMS320E15, TMS320LC15, TMS320P15 DIGITAL SIGNAL PROCESSORS

SPRS009C ± JANUARY 1987 ± REVISED JULY 1991

Program Bus

	12 LSB
	MUX		12
12	12		12
	12

	PC (12)
	12		Instruction
	12		Instruction
	12			16
		Address		16
		Address	Program	MUX	D15-D0
			ROM/EPROM		D15-D0
	Stack		ROM/EPROM
	Stack		(4K Words)
	4 × 12		(4K Words)
	4 × 12
Program Bus

						16	16
				Data Bus
		16		7		16	16
	ARP	AR0 (16)			DP		T(16)
	ARP	AR1 (16)			DP	Shifter	T(16)
		AR1 (16)				(0±16)
			8			(0±16)		16
			8	8			Multiplier	16
				8			Multiplier
				MUX		32	P(32)
				MUX
				8			32
				8			32
				Address			MUX
						32	32
				Data RAM
Legend:				(256 Words)		ALU (32)
Legend:
ACC = Accumulator
ACC = Accumulator				Data			32
ALU = Arithmetic Logic Unit				Data			32
ALU = Arithmetic Logic Unit
ARP = Auxiliary Register Pointer
AR0	= Auxiliary Register 0					ACC (32)
AR1	= Auxiliary Register 1
DP	= Data Page Pointer					32	32
P	= P Register					32
P	= P Register
PC	= Program Counter
T	= T Register				Shifter (0,1,4)
					Shifter (0,1,4)
				16	16		16

Data Bus

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001

TMS320C15, TMS320E15, TMS320LC15, TMS320P15

DIGITAL SIGNAL PROCESSORS

SPRS009C± JANUARY 1987 ± REVISED JULY 1991

TERMINAL FUNCTIONS (TMS320C15/E15/LC15/P15)²

		NAME	I/O³	DEFINITION
	A11-A0/PA2-PA0		O	External address bus. I/O port address multiplexed over PA2-PA0.
			I	External polling input
	BIO
	CLKOUT		O	System clock output, 1/4 crystal/CLKIN frequency
	D15-D0		I/O	16-bit parallel data bus
			O	Data enable for device input data on D15-D0
	DEN
			I	External interrupt input
	INT
			I	Memory mode select pin. High selects microcomputer mode. Low selects microprocessor mode.
	MC/MP
			O	Memory enable indicates that D15-D0 will accept external memory instruction.
	MEN
	NC		O	No connection
			I	Reset for initializing the device
	RS
	VCC		I	+ 5 V supply
	VSS		I	Ground
	WE		O	Write enable for device output data on D15-D0
	X1		O	Crystal output for internal oscillator
	X2/CLKIN		I	Crystal input internal oscillator or external system clock input

²	See EPROM programming section.
³	Input/Output/High-impedance state.

54	POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001

TMS320C15, TMS320E15, TMS320P15

DIGITAL SIGNAL PROCESSORS

SPRS009C ± JANUARY 1987 ± REVISED JULY 1991

electrical specifications

This section contains the electrical specifications for the ′C15/E15/P15 digital signal processors, including test parameter measurement information. Parameters with PP subscripts apply only to the ′E15/P15 in the EPROM programming mode (see Note 11).

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)²

Supply voltage range, VCC (see Note 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . ±0.3 V to 7	V
Supply voltage range, VPP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. ±0.6 V to 14	V
Input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. ±0.3 V to 14	V
Output voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . ±0.3 V to 7	V
Continuous power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . . 0.5 mW
Operating free-air temperature: L suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . 0°C to 70°C
A suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	± 40°C to 85°C
Storage temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	±55 °C to 150 °C

²Stresses beyond those listed under ªAbsolute Maximum Ratingsº may cause permanent damage to the device. This is a stress ratingonly, and functional operation of the device at these or any other conditions beyond those indicated in the ªRecommended Operating Conditionsº section of this specification is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTE 6: All voltage values are with respect to VSS.

recommended operating conditions

			MIN	NOM	MAX	UNIT

VCC	Supply voltage	EPROM devices	4.75	5	5.25	V

		All other devices	4.5	5	5.5	V
		All other devices	4.5	5	5.5	V

VPP	Supply voltage (see Note 11)		12.25	12.5	12.75	V
VSS	Supply voltage			0		V
VIH	High-level input voltage	CLKIN	3			V

		All remaining inputs	2			V
		All remaining inputs	2			V

					0.6	V
VIL	Low-level input voltage	MC/MP			0.6	V
VIL	Low-level input voltage	All remaining inputs			0.8	V
		All remaining inputs			0.8	V

IOH	High-level output current, all outputs				± 300	A
IOL	Low-level output current (All outputs except for TMS320LC15)				2	mA
TA	Operating free-air temperature	L suffix	0		70	°C

		A suffix	± 40		85	°C
		A suffix	± 40		85	°C

NOTE 11: VPP can be applied only to programming pins designed to accept VPP as an input. During programming the total supply current is IPP + ICC.

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001

TMS320C15, TMS320E15, TMS320P15

DIGITAL SIGNAL PROCESSORS

SPRS009C± JANUARY 1987 ± REVISED JULY 1991

electrical characteristics over specified temperature range (unless otherwise noted)

	PARAMETER			TEST CONDITIONS				MIN	TYP²	MAX	UNIT
VOH	High-level output voltage			IOH = MAX				2.4	3		V
VOH	High-level output voltage			IOH = 20 A (see Note 8)				VCC ± 0.4			V
				IOH = 20 A (see Note 8)				VCC ± 0.4			V
VOL	Low-level output voltage			IOL = MAX					0.3	0.5	V
IOZ	Off-state output current			VCC = MAX			VO = 2.4 V			20	A
IOZ	Off-state output current			VCC = MAX			VO = 0.4 V			± 20	A
							VO = 0.4 V			± 20
II	Input current			VI = VSS to VCC			All inputs except CLKIN			±20	A

							CLKIN			±50
							CLKIN			±50

			TMS320C15	f = 20.5 MHz, VCC = 5.5 V, TA = 0°C to 70°C					45	55
ICC³	Supply current		TMS320C15-25	f = 25.6 MHz, VCC = 5.5 V, TA = 0°C to 70°C					50	65	mA
ICC³	Supply current		TMS320E15	f = 20.5 MHz, VCC = 5.25 V, TA = ± 40°C to 85°C					55	75	mA
			TMS320E15	f = 20.5 MHz, VCC = 5.25 V, TA = ± 40°C to 85°C					55	75
			TMS320E15-25	f = 25.6 MHz, VCC = 5.25 V, TA = 0°C to 70°C					65	85
Ci	Input capacitance		Data bus						25³		pF
Ci	Input capacitance		All other	f = 1 MHz, all other pins 0 V					15³		pF
			All other						15³
Co	Output capacitance		Data bus						25³		pF
			Data bus						25³
			All others						10³
			All others						10³
² All typical values are at V		CC	= 5 V, T = 70°C and are used for thermal resistance calculations.
³ I		CC	A
³ I	characteristics are inversely proportional to temperature. For I				CC	dependence on temperature, frequency, and loading, see Figure 3.
CC					CC

NOTE 7: This voltage specification is included for interface to HC logic. However, note that all of the other timing parameters defined in this data sheet are specified for TTL logic levels and will differ for HC logic levels.

CLOCK CHARACTERISTICS AND TIMING

The TMS320C15/E15/P15 can use either its internal oscillator or an external frequency source for a clock.

internal clock option

The internal oscillator is enabled by connecting a crystal across X1 and X2/CLKIN (see Figure 1). The frequency of CLKOUT is one-fourth the crystal fundamental frequency. The crystal should be fundamental mode, and parallel resonant, with an effective series resistance of 30 ohms, a power dissipation of 1 mW, and should be specified at a load capacitance of 20 pF.

PARAMETER		TEST CONDITIONS	MIN	NOM	MAX	UNIT

	TMS320C15	TA = 0°C to 70°C	6.7		20.5
Crystal frequency, fx	TMS320E15/P15	TA = ± 40°C to 85°C	6.7		20.5	MHz
	TMS320C15-25/E15-25	TA = 0°C to 70°C	6.7		25.6
C1, C2		TA = 0°C to 70°C		10		pF

56	POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001

TMS320C15, TMS320E15, TMS320P15

DIGITAL SIGNAL PROCESSORS

SPRS009C ± JANUARY 1987 ± REVISED JULY 1991

external clock option

An external frequency source can be used by injecting the frequency directly into X2/CLKIN with X1 left unconnected. The external frequency injected must conform to the specifications listed in the table below.

switching characteristics over recommended operating conditions

		PARAMETER	TEST CONDITIONS	TMS320C15/E15/P15			TMS320C15-25/E15-25			UNIT

				MIN	NOM	MAX	MIN	NOM	MAX
				MIN	NOM	MAX	MIN	NOM	MAX

t		CLKOUT cycle time³		195.12	200		156.25	160		ns
c(C)
tr(C)		CLKOUT rise time	RL = 825 Ω,		10²			10²		ns
tf(C)		CLKOUT fall time	RL = 825 Ω,		8²			8²		ns
tf(C)		CLKOUT fall time	CL = 100 pF		8²			8²		ns
tw(CL)		Pulse duration, CLKOUT low	(see Figure 2)		92²			72²		ns
tw(CL)		Pulse duration, CLKOUT low			92²			72²		ns
tw(CH)		Pulse duration, CLKOUT high			90²			70²		ns
t		Delay time, CLKIN↑ to CLKOUT↓		25²		60²	25²		50²	ns
d(MCC)
² Values derived from characterization data and not tested.
³ t	is the cycle time of CLKOUT, i.e., 4t		(4 times CLKIN cycle time if an external oscillator is used).
c(C)		c(MC)

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001

TMS320C15, TMS320E15, TMS320P15

DIGITAL SIGNAL PROCESSORS

SPRS009C± JANUARY 1987 ± REVISED JULY 1991

timing requirements over recommended operating conditions

		TMS320C15/E15/P15			TMS320C15-25/E15-25			UNIT

		MIN	NOM	MAX	MIN	NOM	MAX
		MIN	NOM	MAX	MIN	NOM	MAX

tc(MC)	Master clock cycle time	48.78	50	150	39.06	40	150	ns
t	Rise time, master clock input		5²	10²		5²	10²	ns
r(MC)
t	Fall time, master clock input		5²	10²		5²	10²	ns
f(MC)
tw(MCP)²	Pulse duration, master clock	0.4tc(MC)	0.6tc(MC)²		0.45tc(MC)	0.55tc(MC)²		ns
tw(MCL)	Pulse duration, master clock low		20²			15²		ns
tw(MCH)	Pulse duration, master clock high		20²			15²		ns

² Values derived from characterization data and not tested.

MEMORY AND PERIPHERAL INTERFACE TIMING

switching characteristics over recommended operating conditions

PARAMETER

TEST

TMS320C15/E15/P15

TMS320C15-25/E15-25

UNIT

CONDITIONS

MIN

NOM

MAX

MIN

NOM

MAX

td1

Delay time, CLKOUT↓ to

10²

10³

address bus valid

1/4t (C) ± 5²

± 5²

Delay time, CLKOUT↓ to

MEN

↓

1/4t

c(C)

+15

1/4t

c(C)

+12

c(C)

±10²

Delay time, CLKOUT↓ to

MEN

↑

Delay time, CLKOUT↓ to

↓

1/4t

± 5²

1/4t

+15

1/ t

± 5²

1/ t

+12

DEN

c(C)

4 c(C)

Delay time, CLKOUT↓ to

↑

±10²

DEN

Delay time, CLKOUT↓ to

↓

1/2t

± 5²

1/2t

+15

1/2t

± 5²

1/2t

+12

c(C)

Delay time, CLKOUT↓ to

↑

±10²

td8

Delay time, CLKOUT↓ to data bus

1/4tc(C) +65

1/4tc(C) +52

OUT valid

RL = 825 Ω,

Time after CLKOUT↓ that data bus

CL = 100 pF

1/4t

± 5

starts to be driven

(see Figure 2)

c(C)

Time after CLKOUT↓ that

+ 40²

data bus stops being driven

1/4t

d10

(TMS320C15/C15-25 only)

c(C)

Time after CLKOUT↓ that

1/4tc(C) + 70²

1/4tc(C) +70²

td10

data bus stops being driven

(TMS320E15/E15-25 only)

Data bus OUT valid after CLKOUT↓

1/4tc(C) ± 10

Address hold time after

↑,

th(A-WMD)

MEN

0²

2²

0²

2²

or DEN↑ (see Note 15)

tsu(A-MD)

Address bus setup time prior to

1/4tc(C) ± 45

1/4tc(C) ± 35

DEN↓

² Values derived from characterization data and not tested.

NOTE 14: Address bus will be valid upon WE↑, MEN↑, or

DEN

↑.

timing requirements over recommended operating conditions

TEST

TMS320C15/E15/P15

TMS320C15-25/E15-25

UNIT

CONDITIONS

MIN

NOM

MAX

MIN

NOM

MAX

tsu(D)

Setup time, data bus valid prior to CLKOU-

RL = 825 Ω,

T↓

CL = 100 pF

Hold time, data bus held valid after

(see Figure 2)

th(D) CLKOUT↓ (see Note 9)

NOTE 9: Data may be removed from the data bus upon MEN↑ or DEN↑ preceding CLKOUT↓.

58	POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001

TMS320C15, TMS320E15, TMS320P15

DIGITAL SIGNAL PROCESSORS

SPRS009C ± JANUARY 1987 ± REVISED JULY 1991

RESET (RS) TIMING

switching characteristics over recommended operating conditions

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Delay time,

↑,

↑, and

↑ from

RL = 825 Ω,

1/ t

+ 50²

d11

DEN

MEN

CL = 100 pF

2 c(C)

+ 50²

dis(R)

Data bus disable time after RS

(see Figure 2)

1/ t

4 c(C)

² Values derived from characterization data and not tested.

timing requirements over recommended operating conditions

TMS320C15/E15/P15

TMS320C15-25/E15-25

UNIT

MIN

NOM

MAX

MIN

NOM

MAX

tsu(R)

Reset

(RS)

setup time prior to CLKOUT (see Note 10)

tw(R)

pulse duration

5tc(C)

NOTE 10: RS can occur anytime during a clock cycle. Time given is minimum to ensure synchronous operation.

INTERRUPT (INT) TIMING

timing requirements over recommended operating conditions

TMS320C15/E15/P15

TMS320C15-25/E15-25

UNIT

MIN

NOM MAX

MIN

NOM

MAX

tf(INT)

Fall time,

INT

tw(INT)

Pulse duration,

tc(C)

INT

tsu(INT)

Setup time,

↓ before CLKOUT↓

INT

IO (BIO) TIMING

timing requirements over recommended operating conditions

TMS320C15/E15/P15

TMS320C15-25/E15-25

UNIT

MIN

NOM

MAX

MIN

NOM

MAX

tf(IO)

Fall time,

BIO

tw(IO)

Pulse duration,

tc(C)

BIO

tsu(IO)

Setup time,

↓ before CLKOUT↓

BIO

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001

TMS320C15, TMS320E15, TMS320P15

DIGITAL SIGNAL PROCESSORS

SPRS009C± JANUARY 1987 ± REVISED JULY 1991

TIMING DIAGRAMS

Timing measurements are referenced to and from a low voltage of 0.8 volts and a high voltage of 2.0 volts, unless otherwise noted.

clock timing

tr(MC)	tw(MCH)	tw(MCP)²
tc(MC)		tw(MCP)²
tc(MC)
X2/CLKIN
tw(MCL)
tf(MC)		tw(CH)
td(MCC)²		tw(CH)
td(MCC)²
CLKOUT
tf(C)		tr(C)

tw(CL)

tc(C)

² td(MCC) and tw(MCP) are referenced to an intermediate level of 1.5 V on the CLKIN waveform.

memory read timing

	tc(C)
CLKOUT
td2
td3
MEN
td1	tsu(A-MD)	th(A-WMD)
td1		th(A-WMD)
A11-A0	Address Bus Valid
	tsu(D)	th(D)
		th(D)
D15-D0	Instruction Valid

60	POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001

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