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TMS320C10, TMS320C10-14, TMS320C10-25

DIGITAL SIGNAL PROCESSORS

SPRS009C ± JANUARY 1987 ± REVISED JULY 1991

Key Features: TMS320C10

+5 V

GND

• Instruction Cycle Timing

160-ns (TMS320C10-25)

200-ns (TMS32010)

280-ns (TMS320C10-14)

144-Word RAM

• 144 Words of On-Chip Data RAM

Interrupt

Data (16)

• 1.5K Words On-Chip Program ROM

1.5K-Word ROM

• External Memory Expansion up to 4K

32-Bit ALU/ACC

Words at Full Speed

Multiplier

• 16 × 16-Bit Multiplier With 32-Bit Product

Address (12)

• 0 to 16-Bit Barrel Shifter

Shifters

•On-Chip Clock Oscillator

•Device Packaging:

Ð40-Pin DIP

Ð44-Lead PLCC

•Single 5-V Supply

•Operating Free-Air Temperature Range

. . . 0°C to 70°C

		TMS320C10													TMS320C10
		N/JD Package											FN/FZ Package
		(Top View)													(Top View)
									INT	RS		MC/MP A0/PA0 A1/PA1 V A2/PA2 A3 A4 A5 A6
A1/PA1			1	40	A2/PA2				INT	RS		MC/MP A0/PA0 A1/PA1 V A2/PA2 A3 A4 A5 A6
A1/PA1			1	40	A2/PA2														SS
A0/PA0			2	39	A3
A0/PA0			2	39	A3
MC/MP			3	38	A4
	RS		4	37	A5		6			5	4			3		2		1 44 43 42 41 40
	INT		5	36	A6	CLKOUT		7										39			A7
	INT		5	36	A6	CLKOUT		7										39			A7
CLKOUT			6	35	A7	X1		8										38			A8
CLKOUT			6	35	A7	X1		8										38			A8
	X1		7	34	A8	X2/CLKIN		9										37			MEN
X2/CLKIN			8	33	MEN	BIO		10										36			DEN
X2/CLKIN			8	33	MEN	BIO		10										36			DEN
BIO			9	32	DEN	NC		11										35			WE
BIO			9	32	DEN	NC		11										35			WE
VSS			10	31	WE	VSS		12										34			VCC
				31

	D8		11	30	VCC	D8		13										33			A9
	D9		12	29	A9	D9		14										32			A10
	D9		12	29	A9	D9		14										32			A10
D10			13	28	A10	D10		15										31			A11
D10			13	28	A10	D10		15										31			A11
D11			14	27	A11	D11		16										30			D0
D11			14	27	A11	D11		16										30			D0
D12			15	26	D0	D12		17										29			D1
D12			15	26	D0	D12		17										29			D1
D13			16	25	D1		18 19 20							21 22 23 24 25 26 27 28
D14			17	24	D2		18 19 20							21 22 23 24 25 26 27 28
D14			17	24	D2
	D7		19	22	D4				V	D13		D14			D15		D7		D6 D5 D4 D3 D2 V
D15			18	23	D3				CC											CC
D15			18	23	D3
	D6		20	21	D5

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001

TMS320C10, TMS320C10-14, TMS320C10-25

DIGITAL SIGNAL PROCESSORS

SPRS009C± JANUARY 1987 ± REVISED JULY 1991

			TERMINAL FUNCTIONS

	NAME	I/O²	DEFINITION
A11-A0/PA2-PA0		O	External address bus. I/O port address multiplexed over PA2-PA0.
		I	External polling input
BIO		I	External polling input
CLKOUT		O	System clock output, 1/4 crystal/CLKIN frequency
D15-D0		I/O	16-bit parallel data bus
		O	Data enable for device input data on D15-D0
DEN		O	Data enable for device input data on D15-D0
		I	External interrupt input
INT		I	External interrupt input
		I	Memory mode select pin. High selects microcomputer mode. Low selects microprocessor mode.
MC/MP		I
		O	Memory enable indicates that D15-D0 will accept external memory instruction.
MEN		O
NC		O	No connection
		I	Reset for initializing the device
RS		I	Reset for initializing the device
VCC		I	+ 5 V supply
VSS		I	Ground
WE		O	Write enable for device output data on D15-D0
X1		O	Crystal output for internal oscillator
X2/CLKIN		I	Crystal input internal oscillator or external system clock input

² Input/Output/High-impedance state.

12	POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001

functional block diagram

		X1
	CLKOUT	X2/CLKIN
WE		16
DEN		16
DEN		Controller
MEN		Controller
MEN
BIO
MC/MP
INT
RS
A11-A0/	MUX	3
A11-A0/
PA2-PA0
		3

TMS320C10, TMS320C10-14, TMS320C10-25 DIGITAL SIGNAL PROCESSORS

SPRS009C ± JANUARY 1987 ± REVISED JULY 1991

Program Bus

	12 LSB
	MUX		12
12	12		12
	12

	PC (12)
	12		Instruction
	12		Instruction
	12			16
		Address		16
		Address	Program	MUX	D15-D0
			Program
			ROM/EPROM
	Stack		ROM/EPROM
	Stack		(1.5K Words)
	4 × 12
Program Bus

						16	16
				Data Bus
		16		7		16	16
	ARP	AR0 (16)			DP		T(16)
	ARP	AR1 (16)			DP	Shifter	T(16)
		AR1 (16)				(0±16)
			8			(0±16)		16
			8	8			Multiplier	16
				8			Multiplier
				MUX		32	P(32)
				MUX
				8			32
				8			32
				Address			MUX
						32	32
				Data RAM
Legend:				(144 Words)		ALU (32)
Legend:
ACC = Accumulator
ACC = Accumulator				Data			32
ALU = Arithmetic Logic Unit				Data			32
ALU = Arithmetic Logic Unit
ARP = Auxiliary Register Pointer
AR0	= Auxiliary Register 0					ACC (32)
AR1	= Auxiliary Register 1
DP	= Data Page Pointer					32	32
P	= P Register					32
P	= P Register
PC	= Program Counter
T	= T Register				Shifter (0,1,4)
					Shifter (0,1,4)
				16	16		16

Data Bus

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001

TMS320C10, TMS320C10-14, TMS320C10-25

DIGITAL SIGNAL PROCESSORS

SPRS009C± JANUARY 1987 ± REVISED JULY 1991

electrical specifications

This section contains the electrical specifications for all speed versions of the ′C10 Digital Signal Processors, including test parameter measurement information.

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)²

Supply voltage range VCC (see Note 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . ±0.3 V to 7 V
Input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . ±0.3 V to 7 V
Output voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . ±0.3 V to 7 V
Continuous power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . . 0.5 mW
Operating free-air temperature: L suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . 0°C to 70°C
A suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	± 40°C to 85°C
Storage temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	±55 °C to 150 °C

²Stresses beyond those listed under ªAbsolute Maximum Ratingsº may cause permanent damage to the device. This is a stress ratingonly, and functional operation of the device at these or any other conditions beyond those indicated in the ªRecommended Operating Conditionsº section of this specification is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTE 6: All voltage values are with respect to VSS.

recommended operating conditions

			MIN	NOM	MAX	UNIT

VCC	Supply voltage		4.5	5	5.25	V
VSS	Supply voltage			0		V
VIH	High-level input voltage	CLKIN	3			V

		All remaining inputs	2			V
		All remaining inputs	2			V

					0.6	V
VIL	Low-level input voltage	MC/MP			0.6	V

		All remaining inputs			0.8	V
		All remaining inputs			0.8	V

IOH	High-level output current, all outputs				±300	A
IOL	Low-level output current				2	mA
TA	Operating free-air temperature	L suffix	0		70	°C

		A suffix	± 40		85	°C
		A suffix	± 40		85	°C

14	POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001

TMS320C10, TMS320C10-14, TMS320C10-25

DIGITAL SIGNAL PROCESSORS

SPRS009C ± JANUARY 1987 ± REVISED JULY 1991

electrical characteristics over specified temperature range (unless otherwise noted)

	PARAMETER				TEST CONDITIONS		MIN	TYP²	MAX	UNIT
VOH	High-level output voltage				IOH = MAX		2.4	3		V
VOH	High-level output voltage				I = 20 µA (see Note 7)		V	± 0.4³		V
					OH		CC
VOL	Low-level output voltage				IOL = MAX			0.3	0.5	V
IOZ	Off-state output current				VCC = MAX	VO = 2.4 V			20	µA
IOZ	Off-state output current				VCC = MAX	VO = 0.4 V			± 20	µA
						VO = 0.4 V			± 20
II	Input current				VCC = VSS to VCC	All inputs except CLKIN			±20	µA

						CLKIN			±50
						CLKIN			±50

Ci	Input capacitance			Data bus				25³		pF
Ci	Input capacitance			All others	f = 1 MHz, all other pins 0 V			15³		pF
				All others				15³
Co	Output capacitance			Data bus				25³		pF
				Data bus				25³
				All others				10³
				All others				10³
² All typical values are at V		CC	= 5 V, T = 25°C.
		CC		A

³ Values derived from characterization data and not tested.

NOTE 7: This voltage specification is included for interface to HC logic. However, note that all of the other timing parameters defined in this data sheet are specified for TTL logic levels and will differ for HC logic levels.

INTERNAL CLOCK OPTION

X1 X2/CLKIN

Crystal

Figure 1. Internal Clock Option

PARAMETER MEASUREMENT INFORMATION

2.15 V

RL = 825 Ω

From Output

Under Test

Test

Point

CL = 100 pF

Figure 2. Test Load Circuit

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001

TMS320C10, TMS320C10-25

DIGITAL SIGNAL PROCESSORS

SPRS009C± JANUARY 1987 ± REVISED JULY 1991

electrical characteristics over specified temperature range (unless otherwise noted)

	PARAMETER		TEST CONDITIONS			MIN	TYP²	MAX	UNIT
				(SEE FIGURE 2)


ICC³	Supply current	TMS320C10	f = 20.5 MHz, VCC = 5.5 V, TA = ± 40°C to 85°C				33	55	mA
		TMS320C10-25	f = 25.6 MHz, VCC = 5.5 V TA = ± 0°C to 70°C				40	65

² All typical values are at T = 70°C and are used for thermal resistance calculations.
³ I	A
	characteristics are inversely proportional to temperature. For I			CC	dependence on temperature, frequency, and loading.
CC

CLOCK CHARACTERISTICS AND TIMING

The ′C10/C10-25 can use either its internal oscillator or an external frequency source for a clock.

internal clock option

The internal oscillator is enabled by connecting a crystal across X1 and X2/CLKIN (see Figure 1). The frequency of CLKOUT is one-fourth the crystal fundamental frequency. The crystal should be fundamental mode, and parallel resonant, with an effective series resistance of 30 ohms, a power dissipation of 1 mW, and should be specified at a load capacitance of 20 pF.

PARAMETER		TEST CONDITIONS	MIN	NOM	MAX	UNIT

Crystal frequency, fx	TMS320C10	TA = ± 40°C to 85°C	6.7		20.5	MHz
Crystal frequency, fx	TMS320C10-25	TA = 0°C to 70°C	6.7		25.6	MHz
	TMS320C10-25	TA = 0°C to 70°C	6.7		25.6
C1, C2		TA = ± 40°C to 85°C		10		pF

external clock option

An external frequency source can be used by injecting the frequency directly into X2/CLKIN with X1 left unconnected. The external frequency injected must conform to the specifications listed in the table below.

switching characteristics over recommended operating conditions

		PARAMETER	TEST CONDITIONS		TMS320C10		TMS320C10-25			UNIT

				MIN	NOM	MAX	MIN	NOM	MAX
				MIN	NOM	MAX	MIN	NOM	MAX

t		CLKOUT cycle time§		195.12	200		156.25	160		ns
c(C)
tr(C)		CLKOUT rise time	RL = 825 Ω,		10¶			10¶		ns
tf(C)		CLKOUT fall time	RL = 825 Ω,		8¶			8¶		ns
tf(C)		CLKOUT fall time	CL = 100 pF		8¶			8¶		ns
t		Pulse duration, CLKOUT low	(see Figure 2)		92¶			72¶		ns
w(CL)
tw(CH)		Pulse duration, CLKOUT high			90¶			70¶		ns
t		Delay time, CLKIN↑ to CLKOUT↓		25¶		60¶	25		50¶	ns
d(MCC)
§ t	is the cycle time of CLKOUT, i.e., 4t		(4 times CLKIN cycle time if an external oscillator is used).
c(C)		c(MC)

¶ Values derived from characterization data and not tested.

timing requirements over recommended operating conditions

		TMS320C10				TMS320C10-25		UNIT

		MIN	NOM	MAX	MIN	NOM	MAX
		MIN	NOM	MAX	MIN	NOM	MAX

t	Master clock cycle time	48.78	50	150	39.06	40	150¶	ns
c(MC)
tr(MC)	Rise time, master clock input		5¶	10¶		5¶	10¶	ns
t	Fall time, master clock input		5¶	10¶		5¶	10¶	ns
f(MC)
tw(MCP)	Pulse duration, master clock	0.4tc(MC)¶	0.6tc(MC)¶		0.45tc(MC)¶ 0.55tc(MC)¶			ns
tw(MCL)	Pulse duration, master clock low		20¶			15¶		ns
tw(MCH)	Pulse duration, master clock high		20¶			15¶		ns

¶ Values derived from characterization data and not tested.

16	POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001

TMS320C10, TMS320C10-25

DIGITAL SIGNAL PROCESSORS

SPRS009C ± JANUARY 1987 ± REVISED JULY 1991

MEMORY AND PERIPHERAL INTERFACE TIMING

switching characteristics over recommended operating conditions

PARAMETER

TEST

TMS320C10

TMS320C10-25

UNIT

CONDITIONS

MIN

TYP

MAX

MIN

TYP

MAX

td1

Delay time, CLKOUT↓ to

10²

address bus valid

td2

Delay time, CLKOUT↓

1/4tc(C)

± 5²

1/4tc(C) + 15

1/4tc(C) ± 5²

1/4tc(C) + 12

to MEN↓

td3

Delay time, CLKOUT↓

±10²

to MEN↑

td4

Delay time, CLKOUT↓

1/4tc(C)

± 5² 1 /4tc(C) + 15

1/4tc(C) ± 5²

1/4tc(C) + 12

to DEN↓

td5

Delay time, CLKOUT↓

±10²

to DEN↑

± 5²

1/2t ± 5²

Delay time, CLKOUT↓ to

↓

RL = 825 Ω

1/2t

c(C)

+ 15

1/2t

+ 12

c(C)

CL = 100 pF,

±10²

Delay time, CLKOUT↓ to

↑

(see Figure 2)

Delay time, CLKOUT↓ to data

1/4t

c(C)

+ 65

1/4t

+ 52²

bus OUT valid

c(C)

td9

Time after CLKOUT↓ that data

1/4tc(C)

± 5²

1/4tc(C) ± 5²

bus starts to be driven

Time after CLKOUT↓ that data

1/4t

+ 40²

1/4t

+ 40²

d10

bus stops being driven

c(C)

Data bus OUT valid after

1/4tc(C)

± 10

1/4tc(C) ± 10

CLKOUT↓

Address hold time after

↑,

th(A-WMD)

±10²

MEN↑, or DEN↑ (see Note 8)

tsu(A-MD)

Address bus setup time prior

1/4tc(C)

± 45

1/4tc(C) ± 35

to MEN↓ or

DEN

↓

² Values derived from characterization data and not tested. NOTE 8: For interfacing I/O devices, see Figure 3.

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001

TMS320C10, TMS320C10-25

DIGITAL SIGNAL PROCESSORS

SPRS009C± JANUARY 1987 ± REVISED JULY 1991

timing requirements over recommended operating conditions

		TEST CONDITION		TMS320C10	TMS320C10-25		UNIT

			MIN	NOM MAX	MIN	NOM MAX
			MIN	NOM MAX	MIN	NOM MAX

tsu(D) Setup time, data bus valid prior to CLKOUT↓		RL = 825 Ω,	50		40		ns
th(D)	Hold time, data bus held valid after CLKOUT↓	CL = 100 pF	0		0		ns
th(D)	(see Note 9)	(see Figure 2)	0		0		ns
	(see Note 9)

NOTE 9: Data may be removed from the data bus upon MEN↑ or DEN↑ preceding CLKOUT↓.

SUGGESTED I/O DECODE CIRCUIT

The circuit shown in Figure 3 is a design example for interfacing I/O devices to the ′C10/C10-25. This circuit decodes the address for output operations using the OUT instruction. The same circuit can be used to decode input and output operations if the inverter ('ALS04) is replaced with a NAND gate and both DEN and WE are connected. Inputs and outputs can be decoded at the same port provided the output of the decoder ('AS137) is gated with the appropriate signal (DEN or WE) to select read or write (using an 'ALS32). Access times can be increased when the circuit shown in Figure 3 is repeated to support IN instructions with DEN connected rather than WE.

The table write (TBLW) function requires a different circuit. A detailed discussion of an example circuit for this function is described in the application report, ªInterfacing External Memory to the TMS32010º, published in the book, Digital Signal Processing Applications with the TMS320 Family (SPRA012A).

TMS320C10	74ALS04		74AS137
	74ALS04
32	4	GL	Y0	15
WE		GL
WE				14
			Y1	14
			Y1
2	1	A	Y2	13
PA0	2	A
1	2	B	Y3	12
PA1		B	Y4
PA1
40	3	C		11
40	3			11
PA2			Y5
			Y5	10
			Y6	10
	6		Y6
	6	G1	Y7	9
	VCC	G1	Y7	7	I/O Device
	5	G2			I/O Device
	5

Figure 3. I/O Decode Circuit

18	POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001

TMS320C10, TMS320C10-25

DIGITAL SIGNAL PROCESSORS

SPRS009C ± JANUARY 1987 ± REVISED JULY 1991

RESET (RS) TIMING

switching characteristics over recommended operating conditions

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Delay time,

↑,

↑, and

↑ from

RL 825 Ω,

1/2t

+50²

d11

DEN

MEN

c(C)

CL = 100 pF,

dis(R)

Data bus disable time after

1/4t

c(C)

+50²

(see Figure 2)

² Values derived from characterization data and not tested.

timing requirements over recommended operating conditions

TMS320C10

TMS320C10-25

UNIT

PARAMETER

MIN

NOM

MAX

MIN

NOM

MAX

tsu(R)

Reset

setup time prior to CLKOUT (see Note 10)

(RS)

tw(R)

pulse duration

5tc(C)

NOTE 10: RS can occur anytime during a clock cycle. Time given is minimum to ensure synchronous operation.

INTERRUPT (INT) TIMING

timing requirements over recommended operating conditions

TMS320C10

TMS320C10-25

UNIT

MIN

NOM

MAX

MIN

NOM

MAX

tf(INT)

Fall time,

INT

tw(INT)

Pulse duration,

tc(C)

INT

tsu(INT)

Setup time,

↓ before CLKOUT↓

INT

IO (BIO) TIMING

timing requirements over recommended operating conditions

TMS320C10

TMS320C10-25

UNIT

MIN

NOM

MAX

MIN

NOM

MAX

tf(IO)

Fall time,

BIO

tw(IO)

Pulse duration,

tc(C)

BIO

tsu(IO)

Setup time,

↓ before CLKOUT↓

BIO

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001

TMS320C10-14

DIGITAL SIGNAL PROCESSORS

SPRS009C± JANUARY 1987 ± REVISED JULY 1991

electrical characteristics over specified temperature range (unless otherwise noted)

	PARAMETER	TEST CONDITIONS			MIN	TYP²	MAX	UNIT
ICC³	Supply current	f = 14.4, MHz, VCC = 5.5 V, TA = 0°C to 70°C				28	65	mA
² All typical values are at T = 70°C and are used for thermal resistance calculations.
³ I	A
³ I	characteristics are inversely proportional to temperature; i.e., I		CC	decreases approximately linearly with temperature.
CC			CC

CLOCK CHARACTERISTICS AND TIMING

The TMS320C10-14 can use either its internal oscillator or an external frequency source for a clock.

internal clock option

PARAMETER	TEST CONDITIONS	MIN	NOM	MAX	UNIT

Crystal frequency, fx	TA = 0°C to 70°C	6.7		14.4	MHz
C1, C2	TA = 0°C to 70°C		10		pF

external clock option

switching characteristics over recommended operating conditions

		TEST CONDITIONS	MIN	NOM	MAX	UNIT

t	CLKOUT cycle time§		277.78			ns
c(C)
tr(C)	CLKOUT rise time	RL = 825 Ω,		10		ns
tf(C)	CLKOUT fall time	RL = 825 Ω,		8		ns
		CL = 100 pF,
tw(CL)	Pulse duration, CLKOUT low	(see Figure 2)		131		ns
tw(CH)	Pulse duration, CLKOUT high			129		ns
t	Delay time, CLKIN↑ to CLKOUT↓		25¶		60¶	ns
d(MCC)

§ tc(C) is the cycle time of CLKOUT, i.e., 4tc(MC) (4 times CLKIN cycle time if an external oscillator is used). ¶ Values derived from characterization data and not tested.

timing requirements over recommended operating conditions

				MIN	NOM	MAX	UNIT

tc(MC)	Master clock cycle time			69.5		150	ns
tr(MC)	Rise time, master clock input				5¶	10¶	ns
t	Fall time, master clock input				5¶	10¶	ns
f(MC)
tw(MCP)	Pulse duration, master clock			0.4tc(MC)¶	0.6tc(MC)¶		ns
tw(MCL)	Pulse duration, master clock low, tc(MC) = 50 ns				20¶		ns
t	Pulse duration, master clock high, t	c(MC)	= 50 ns		20¶		ns
w(MCH)		c(MC)

¶ Values derived from characterization data and not tested.

20	POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001

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