35(/,0,1$5< 7(&+1,&$/ '$7$
ADSP-2196
For current information contact Analog Devices at 800/262-5643 |
September 2001 |
|
Serial Peripheral Interface (SPI) Port—Slave Timing
Table 21 and Figure 24 describe SPI port slave operations.
Table 21. Serial Peripheral Interface (SPI) Port—Slave Timing
Parameter |
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Description |
Min |
Max |
Unit |
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Switching Characteristics |
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tDSOE |
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assertion to data out active |
0 |
6 |
ns |
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SPISS |
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tDSDHI |
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deassertion to data high impedance |
0 |
6 |
ns |
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SPISS |
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tDDSPID |
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SCLK edge to data out valid (data out delay) |
0 |
5 |
ns |
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tHDSPID |
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SCLK edge to data out invalid (data out hold) |
0 |
5 |
ns |
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Timing Requirements |
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tSPICHS |
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Serial clock high period |
2tHCLK |
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ns |
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tSPICLS |
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Serial clock low period |
2tHCLK |
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ns |
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tSPICLK |
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Serial clock period |
4tHCLK |
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ns |
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tHDS |
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Last SPICLK edge to |
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not asserted |
2tHCLK |
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ns |
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SPISS |
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tSPITDS |
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Sequential Transfer Delay |
2tHCLK |
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ns |
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tSDSCI |
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assertion to first SPICLK edge |
2tHCLK |
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ns |
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SPISS |
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tSSPID |
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Data input valid to SCLK edge (data input setup) |
1.6 |
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ns |
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tHSPID |
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SCLK sampling edge to data input invalid |
1.6 |
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ns |
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48 |
This information applies to a product under development. Its characteristics and specifications are subject to change with- |
REV. PrA |
|
out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. |
|
35(/,0,1$5< 7(&+1,&$/ '$7$
September 2001 |
For current information contact Analog Devices at 800/262-5643 |
|
ADSP-2196
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W 6 3 , & / 6 |
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Figure 24. Serial Peripheral Interface (SPI) Port—Slave
REV. PrA |
This information applies to a product under development. Its characteristics and specifications are subject to change with- |
49 |
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out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. |
|
35(/,0,1$5< 7(&+1,&$/ '$7$
ADSP-2196
For current information contact Analog Devices at 800/262-5643 |
September 2001 |
|
Universal Asynchronous Receiver-Transmitter (UART) Port—Receive and Transmit Timing
Figure 25 describes UART port receive and transmit operations. The maximum baud rate is HCLK/16. As shown in Figure 25 there is some latency between the generation
internal UART interrupts and the external data operations. These latencies are negligible at the data transmission rates for the UART.
+& / .
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5 ( & ( , 9 ( |
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8 $ 5 7 5 ( & ( , 9 ( % , 7 6 ( 7 % < ' $ 7 $ 6 7 2 3 |
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$ 6 ' $ 7 |
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$ 5 7 7 5 $ 1 6 0 , 7 % ,7 6 ( 7 % < 3 5 2 * 5 $ 0 |
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Figure 25. UART Port—Receive and Transmit Timing
50 |
This information applies to a product under development. Its characteristics and specifications are subject to change with- |
REV. PrA |
|
out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. |
|
35(/,0,1$5< 7(&+1,&$/ '$7$
September 2001 |
For current information contact Analog Devices at 800/262-5643 |
|
ADSP-2196
|
|
|
|
JTAG Test And Emulation Port Timing |
|
||
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Table 22 and Figure 26 describe JTAG port operations. |
|||
Table 22. JTAG Port Timing |
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|||
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Parameter |
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Description |
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Min |
Max |
Unit |
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|||
Switching Characteristics |
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tDTDO |
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TDO Delay from TCK Low |
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4 |
ns |
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tDSYS |
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System Outputs Delay After TCK Low1 |
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0 |
5 |
ns |
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Timing Parameters |
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tTCK |
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TCK Period |
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20 |
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ns |
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tSTAP |
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TDI, TMS Setup Before TCK High |
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4 |
ns |
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tHTAP |
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TDI, TMS Hold After TCK High |
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4 |
ns |
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tSSYS |
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System Inputs Setup Before TCK Low2 |
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4 |
ns |
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tHSYS |
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System Inputs Hold After TCK Low2 |
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5 |
ns |
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tTRSTW |
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Pulsewidth3 |
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4 |
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ns |
TRST |
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1SystemOutputs =DATA15–0, ADDR21–0, MS3–0, RD, WR, ACK, CLKOUT, BG, PF7–0, TIMEXP, DT0, DT1, TCLK0, TCLK1, RCLK0, RCLK1, TFS0, TFS1, RFS0, RFS1, BMS.
2System Inputs = DATA15–0, ADDR21–0, RD, WR, ACK, BR, BG, PF7–0, DR0, DR1, TCLK0, TCLK1, RCLK0, RCLK1, TFS0, TFS1, RFS0, RFS1, CLKIN, RESET.
350 MHz max.
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W 7 & . |
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7 & . |
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W 6 7 |
$ 3 |
W + 7 |
$ 3 |
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7 |
0 6 |
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7 ' , |
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W ' 7 ' 2 |
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7 |
' 2 |
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W6 6 < 6 |
W + 6 < 6 |
6 < 6 7 |
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,1 3 8 7 6 |
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W ' 6 < 6 |
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6 < 6 7 |
( 0 |
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2 8 7 3 8 7 6 |
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Figure 26. JTAG Port Timing
REV. PrA |
This information applies to a product under development. Its characteristics and specifications are subject to change with- |
51 |
|
out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. |
|