35(/,0,1$5< 7(&+1,&$/ '$7$
ADSP-2196
For current information contact Analog Devices at 800/262-5643 |
September 2001 |
|
Serial Port (SPORT) Frame Synch Timing
Table 19 and Figure 22 describe SPORT frame synch operations.
To determine whether communication is possible between two devices at clock speed n, the following specifications must be confirmed: 1) frame sync delay and frame sync setup and hold, 2) data delay and data setup and hold, and 3) R/TCLK width.
Table 19. Serial Port (SPORT) Frame Synch Timing
Parameter |
Description |
Min |
Max |
Unit |
|
|
|
|
|
|
|
|
|
|
Switching Characteristics |
|
|
|
|
|
|
|
|
|
tHOFSE |
RFS Hold after RCLK (Internally Generated RFS)1 |
|
12.4 |
ns |
tHOFSI |
TFS Hold after TCLK (Internally Generated TFS)1 |
|
12.2 |
ns |
tDDTENFS |
Data Enable from late FS or MCE = 1, MFD = 02 |
|
4.7 |
ns |
tDDTLFSE |
Data Delay from Late External TFS or External RFS with |
|
4.7 |
ns |
|
MCE = 1, MFD = 03 |
|
|
|
tHDTE |
Transmit Data Hold after TCLK (external clk)1 |
|
12.4 |
ns |
tHDTI |
Transmit Data Hold after TCLK (internal clk)1 |
0 |
12.2 |
ns |
tDDTE |
Transmit Data Delay after TCLK (external clk)1 |
0 |
12.2 |
ns |
tDDTI |
Transmit Data Delay after TCLK (internal clk)1 |
0 |
11.1 |
ns |
Timing Requirements |
|
|
|
|
|
|
|
|
|
tSFSE |
TFS/RFS Setup before TCLK/RCLK (external clk)3 |
–0.6 |
TBD |
ns |
tSFSI |
TFS/RFS Setup before TCLK/RCLK (internal clk)3 |
–0.6 |
TBD |
ns |
1Referenced to drive edge.
2MCE = 1, TFS enable and TFS valid follow tDDTLFSE and tDDTENFS. 3Referenced to sample edge.
44 |
This information applies to a product under development. Its characteristics and specifications are subject to change with- |
REV. PrA |
|
out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. |
|
35(/,0,1$5< 7(&+1,&$/ '$7$
September 2001 |
For current information contact Analog Devices at 800/262-5643 |
|
ADSP-2196
(; 7( 5 1 |
$ / 5 ( & ( ,9( )6 : ,7+ 0 & ( 0 )' |
' 5 , 9 ( |
6 $ 0 3 / ( |
' 5 , 9 ( |
|
5 7 & / . |
|
|
|
W 6 ) 6 ( , |
|
W + 2 ) 6 ( , |
6 ( ( 1 2 7 ( |
) 6 |
|
|
|
W ' ' 7 / ) 6 ( |
|
W ' ' 7 ( , |
|
W ' ' 7 ( 1 ) 6 |
|
W + ' 7 ( , |
|
|
|
|
|
' 5 |
) , 5 6 7 % , 7 |
|
6 ( & 2 1 ' % , 7 |
/$ 7 ( ( ;7 ( 5 1 $ / 7 5 $ 1 60 ,7 ) 6
' 5 , 9 ( |
6 |
$ 0 3 / ( |
' 5 , 9 ( |
5 7 & / .
|
W 6 ) 6 ( , |
W + 2 ) 6 ( |
6 ( ( 1 2 7 ( |
|
|
||
|
|
|
|
|
|
, |
|
) 6 |
|
|
|
|
W ' ' 7 / ) 6 ( |
W ' ' 7 ( , |
|
W ' ' 7 ( 1 ) 6 |
|
W + ' 7 ( , |
|
|
|
|
|
' 7 |
) , 5 6 7 % , 7 |
|
6 ( & 2 1 ' % , 7 |
Figure 22. Serial Port (SPORT) Frame Synch
REV. PrA |
This information applies to a product under development. Its characteristics and specifications are subject to change with- |
45 |
|
out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. |
|
35(/,0,1$5< 7(&+1,&$/ '$7$
ADSP-2196
For current information contact Analog Devices at 800/262-5643 |
September 2001 |
|
Serial Peripheral Interface (SPI) Port—Master Timing
Table 20 and Figure 23 describe SPI port master operations.
Table 20. Serial Peripheral Interface (SPI) Port—Master Timing
Parameter |
|
Description |
Min |
Max |
Unit |
|||
|
|
|
|
|
||||
|
|
|
|
|||||
Switching Characteristics |
|
|
|
|||||
|
|
|
|
|
|
|||
tSDSCIM |
|
|
low to first SCLK edge (x=0 or 1) |
2tHCLK |
|
ns |
||
SPIxSEL |
|
|||||||
tSPICHM |
|
Serial clock high period |
2tHCLK |
|
ns |
|||
tSPICLM |
|
Serial clock low period |
2tHCLK |
|
ns |
|||
tSPICLK |
|
Serial clock period |
4tHCLK |
|
ns |
|||
tHDSM |
|
Last SCLK edge to |
|
high (x=0 or 1) |
2tHCLK |
|
ns |
|
SPIxSEL |
|
|||||||
tSPITDM |
|
Sequential transfer delay |
2tHCLK |
|
ns |
|||
tDDSPID |
|
SCLK edge to data out valid (data out delay) |
0 |
6 |
ns |
|||
tHDSPID |
|
SCLK edge to data out invalid (data out hold) |
0 |
5 |
ns |
|||
Timing Requirements |
|
|
|
|||||
|
|
|
|
|
||||
tSSPID |
|
Data input valid to SCLK edge (data input setup) |
1.6 |
|
ns |
|||
tHSPID |
|
SCLK sampling edge to data input invalid |
1.6 |
|
ns |
|||
46 |
This information applies to a product under development. Its characteristics and specifications are subject to change with- |
REV. PrA |
|
out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. |
|
35(/,0,1$5< 7(&+1,&$/ '$7$
September 2001 |
For current information contact Analog Devices at 800/262-5643 |
|
ADSP-2196
6 3 , [ 6 ( / |
|
|
|
|
|
|
2 8 7 3 8 7 |
|
|
|
|
|
|
[ R U |
|
|
|
|
|
|
|
W 6 ' 6 & , 0 |
W 6 3 , & + 0 |
W 6 3 , & / 0 |
W 6 3 , & / . |
W + ' 6 0 |
W 6 3 , 7 ' 0 |
6 & / . |
|
|
|
|
|
|
& 3 2 / |
|
|
|
|
|
|
2 8 7 3 8 7 |
|
|
|
|
|
|
|
W 6 3 , & / 0 |
W 6 3 , & + 0 |
|
|
|
|
6 & / . |
|
|
|
|
|
|
& 3 2 / |
|
|
|
|
|
|
2 8 7 3 8 7 |
|
|
|
|
|
|
|
|
|
W ' ' 6 3 , ' |
W + ' 6 3 , ' |
|
|
0 2 6 , |
|
0 6 % |
|
/ 6 % |
|
|
2 8 7 3 8 7 |
|
|
|
|||
|
|
|
|
|
||
&3+$ |
W 6 6 3 , ' |
|
W + 6 3 , ' |
W 6 6 3 , ' |
W + 6 3 , ' |
|
|
|
|
||||
0 ,6 2 |
0 6 % |
|
|
/ 6 % |
|
|
, 1 3 8 7 |
9 $ / ,' |
|
9 |
$ / , ' |
|
|
0 2 6 , |
|
|
|
|
|
W ' ' 6 3 , ' |
|
W + ' 6 3 , ' |
||
|
|
|
|
|
|
|||||
|
|
0 6 % |
|
|
|
/ 6 % |
||||
2 8 7 3 8 7 |
|
|
|
|
|
|||||
|
|
|
|
|
|
|
||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
&3+$ |
|
|
W 6 6 3 , ' |
|
|
W + 6 3 , ' |
|
|
||
|
|
|
|
|
|
|||||
|
|
|
0 6 % |
|
/ 6 % |
|||||
0 , 6 2 |
|
|
||||||||
|
|
|
|
|
|
|||||
, 1 3 8 7 |
|
|
9 |
$ / ,' |
|
|
|
9 |
$ / , ' |
|
|
|
|
|
|
|
|
|
|
|
|
Figure 23. Serial Peripheral Interface (SPI) Port—Master
REV. PrA |
This information applies to a product under development. Its characteristics and specifications are subject to change with- |
47 |
|
out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. |
|