Теория управления / Л4-Миль-Мур-СА / pics / 6-sequential logic-31
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The result is a sequential device: D-latch
• Used to „freeze“ information when control C = 0
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control |
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D |
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Q |
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data input |
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C |
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C D |
Q |
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R |
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1 0 |
0 |
1 |
1 |
0 |
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1 1 |
1 |
0 |
0 |
1 |
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0 x |
last Q last Q‘ |
1 |
1 |
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S |
T |
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A.J. Han Vinck |
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Ideal timing for a D-latch
D
C 1
0
Q
time
Latch is not clock controlled:= asynchronous
A.J. Han Vinck
Follows D
Stores D
C D Q
1 0 0
1 1 1
0 x last Q
12
A clocked device: Flip-Flop
•Flip-flop
–Output/content changes at times determined by clock
1
0
time
Used in state transition table
clock controlled:= synchronous
A.J. Han Vinck |
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Edge-triggered D Flip Flop(4)
D |
D |
QM |
D |
Q |
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Clock |
latch |
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latch |
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C |
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C |
Q‘ |
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master |
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slave |
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D Q
clk Q‘
Means that the clock rises
Clock‘
Clock
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clock period |
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QM fixed |
time |
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1 |
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D |
CLK |
Q |
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0 |
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0 |
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0 |
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Q=QM |
Q=QM |
1 |
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1 |
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1 |
Q fixed |
Q fixed |
X |
0 |
last Q |
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0 |
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X |
1 |
last Q |
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a new value for D enters |
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take over by slave |
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A.J. Han Vinck |
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14 |
D Q
Edge-triggered D Flip Flop(2)
clk Q‘
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D |
D |
QM |
D |
Q |
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CLK |
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latch |
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latch |
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C |
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C |
Q‘ |
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master |
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slave |
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Clock‘
Clock
QM fixed
time
1
0
Q=QM
1
0
A.J. Han Vinck |
15 |
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D Q
Edge-triggered D Flip Flop(3)
clk Q‘
D |
D |
QM |
D |
Q |
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Clock |
latch |
latch |
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C |
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C |
Q‘ |
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master |
slave |
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QM fixed |
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time |
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Clock‘ |
1 |
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0 |
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Clock |
Q=QM |
Q fixed |
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1 |
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0 |
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take over by slave
A.J. Han Vinck |
16 |
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D Q
Edge-triggered D Flip Flop(4)
clk Q‘
D |
D |
QM |
D |
Q |
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Clock |
latch |
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latch |
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C |
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C |
Q‘ |
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master |
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slave |
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Clock‘
Clock
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clock period |
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QM fixed |
time |
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1 |
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D |
CLK |
Q |
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0 |
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0 |
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0 |
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Q=QM |
Q=QM |
1 |
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1 |
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1 |
Q fixed |
Q fixed |
X |
0 |
last Q |
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0 |
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X |
1 |
last Q |
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a new value for D enters |
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take over by slave |
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A.J. Han Vinck |
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D |
Q |
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Edge-triggered D Flip Flop(5) |
clk |
Q‘ |
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D |
D |
QM |
D |
Q |
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CLK |
latch |
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latch |
Q‘ |
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C |
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C |
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master |
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slave |
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time |
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D |
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D |
CLK |
Q |
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1 |
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CLK |
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0 |
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0 |
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0 |
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1 |
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QM |
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X |
0 |
last Q |
Q |
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X |
1 |
last Q |
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A.J. Han Vinck |
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18 |
A universal flip-flop (called J-K)
D* = Q‘J + QK‘
J |
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D* |
Q |
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D-ff |
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K |
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clk |
Q‘ |
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clk |
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When the clock rises, the output Q := D* Output frozen when JK = 00 Output toggles when JK = 11 Output = J when K = J‘
JK
00 01 11 10
Q 0 0 0 1 1
1 |
1 |
0 |
0 |
1 |
D*
A.J. Han Vinck |
19 |
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Summary of latch and flip-flop
• Latch: can hold a value |
D |
Q |
Q fixed |
C |
Q‘ |
C
• D-Flip-Flop: state/content changes only at the clock’s rising edge
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D |
Q |
clk |
clk |
Q‘ |
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A.J. Han Vinck |
20 |
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