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.pdfDIGITAL SYSTEMS
Sequential Logic Design
December 1, 2010
A.J. Han Vinck
Overview of chapter
•General memory system
•Building
–a memory element
•Latch; flip-flop (D, S-R and J-K)
–a finite state machine with memory elements
•State representations
–timing
–Tree, trellis, state diagram, state table
–State table minimization
• Registers and counters
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Introduction: the concept of memory and sequential
•What do we mean by memory?
A memory should have at least three properties.
1.It should be able to hold a value, for instance 0 or 1.
2.You should be able to read the value that was saved.
3.You should be able to change the value that’s saved.
•What do we mean by sequential circuits?
The outputs of a sequential circuit depend on not only the inputs, but also the state, or the current contents of some memory
– Examples: combination lock, elevators, traffic lights, computers, etc.
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Types of logic: combinational
logic where the output depends on current input only
memoryless
current input
combinational
Output
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Types of logic: sequential Mealy machine
Output depends on current input and memory content
memoryless
current input
combinational
Output
Combinational
logic
memory
memory content changes every T seconds
clock
For binary logic with n memory elements we have 2n states (different contents)
The memory contains all information about the past, necessary to account for the system‘s future behavior
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What is next?
•We develope two basic elements with memory:
- Latch, ( Schnappriegel)
as a building block for the Flip-Flop - Flip-Flop ( a circuit with two stable states )
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We define the clock signal
Example: Clock frequency = # of periods/second = 1 MHz (Herz)clock period 1 Sec
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clock edge |
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clock |
time |
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clock period: T seconds |
change state |
clock frequency: 1/T Hz |
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2 examples of circuits with memory
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Q‘ |
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Bistable circuit |
same |
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1 |
(X•1)‘ = X‘ |
Q
Propagation delay in element
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Q‘ |
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We use the freedom at the NAND input to change the output
R Q
S T
from RS = 01 11 Q = 1 from RS = 10 11 Q = 0
this implementation is the same as used in SRAM
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last Q |
last T |
„state“ |
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NOTE:
from RS = 00 we reach RS = 11 via 01 or 10
Both ways give a different output and thus from 00 to 11 gives unpredictable output
Note: for RS ≠ 00, T = Q‘
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Key idea: avoid 00 as input!
force SR = 11 if output must be fixed ( use C = 0 )
For C = 1, RS = D‘D. For C = 0, RS = 11.
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R |
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C.NAND.D |
C.NAND.D‘ |
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D D‘ |
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