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A slightly fancier counter

•Let’s try to design a slightly different two-bit counter:

–Again, the counter outputs will be 00, 01, 10 and 11.

–Now, there is a single input, X. When X=0, the counter value should increment on each clock cycle. But when X=1, the value should decrement on successive cycles.

•We’ll need two flip-flops again. Here are the four possible states:

The complete state diagram and table

•Here’s the complete state diagram and state table for this circuit.

–Make sure you know how to come up with these – this is a typical sequential design problem!

The counter

clk

clk

4 bit counter (start at 0000)

clk

Q0

Q1

Q2

Note: The Q outputs count downwards, the Q‘ outputs count upwards

4 bit counter with reset

summary

•Important

–Flip-flop derived from D-latch

–Finite state machines: register, counter

–Representation: tree, trellis, state diagram

–State space reduction