Verilog-XL Modeling Style Guide

Modeling Your Hardware (Behavior-Level)

Disabling Named Blocks and Tasks

You can terminate (disable) the activity of a procedure (block or task) before Verilog-XL has executed all the statements with a disable statement. To disable a block (begin-end or fork-join), the block must have a name.

The following example shows you can use a disable statement to model a reset line to a counter. “See Step n” comments in the example correspond to descriptive steps that follow the example.

Example: Disabling named blocks and tasks

module counter(number, reset); output number;

input reset;

reg [15:0] number;

1.If you want to disable a block, you must name the block. This named block, called loop, is an infinite loop that increments a register.

2.Disable a block or task with the disable keyword followed by the block or task name. On the negative edge of reset, Verilog-XL disables the loop block.

Controlling Timing with Delays

You can force Verilog-XL to execute statements after a specified delay using delay controls. A delay control (#) specifies the time from when Verilog-XL encounters a statement to when the statement actually executes. Note that specifying a delay value of zero (#0) causes

Verilog-XL to execute the statement at the end of the current time slot. More than one zero delay causes unpredictable execution order.

The following example shows how you specify behavioral delays to model the delays associated with hardware. “See Step n” comments in the example correspond to descriptive steps that follow the example.

Example: Controlling timing with delays

module DFF(d, clk, clr, q, qb); input clk, d, clr;

Verilog-XL Modeling Style Guide

Modeling Your Hardware (Behavior-Level)

output q, qb; reg q,qb;

wait (clr==1);

join

endmodule // DFF

1.Delay execution of statements with delay control (#) statements. When you use delay control in a begin-end block, Verilog-XL delays execution of the statement until the specified number of time units after the current time.

When clr is not asserted, Verilog-XL assigns the input d to the output q after a delay of 8 units. The inverted output qb receives its value 1 unit after Verilog-XL updates q.

2.When you use delay statements within a fork-join block, Verilog-XL references all delays from when Verilog-XL entered the block.

When clear is asserted, Verilog-XL forces the output q to 0 after 4 time units, and the output qb to 1 one time unit after q transitions.

Controlling Timing with Event Controls

You can control when Verilog-XL executes statements by using event controls. You can specify edge-triggered event controls (@) or level-sensitive event controls (wait). Event controls synchronize statement execution with simulation events, like net or register value changes.

The following example shows how you use event controls to control when Verilog-XL executes statements. “See Step n” comments in the example correspond to descriptive steps that follow the example.

Example: Controlling timing with event controls

module DFF(d, clk, clr, q, qb); input clk, d, clr;

output q, qb; reg q,qb;

Verilog-XL Modeling Style Guide

Modeling Your Hardware (Behavior-Level)

begin

#8 q = d;

#1 qb = ~q; end // always block

wait (clr==1);

join

endmodule // DFF

1.Executes statements at some event in your simulation by using event control (@). Events can be implicit—triggered by a net or register value change—or explicit—triggered by a named event (see “Declaring and Triggering Named Events” on page 48). For implicit events, you can specify a value-change direction with negedge and posedge keywords.

Verilog-XL executes the statements in this block on every positive edge of the clock.

2.Use the wait statement to define level-sensitive triggering. When the specified condition is true, Verilog-XL executes the statements. Verilog-XL executes the statements when clr is low (asserted). When clr is high (not asserted), another wait statement suspends execution of the always block until clr again is asserted. By specifying this second wait statement, execution speed for the simulation is improved.

Declaring and Triggering Named Events

You can model the communication between or synchronization of two or more concurrent processes by defining and triggering named events (explicit events). These events are abstract—they do not correspond to the behavior of a register or wire. Named events also span module boundaries—no port specification is needed.

The following example shows how you use named events to control when Verilog-XL executes statements. “See Step n” comments in the example correspond to descriptive steps that follow the example.

Example: Declaring and triggering named events

module memory_manager(readmem, writemem, clear, address, data); input readmem, writemem, clear, address;

inout data;

reg [7:0] mem [255:0];

wire readmem, writemem. clear; reg [255:0] address;

wire [7:0] data = readmem ? mem[address] : 8’bz; event clear_mem; // See Step 1 integer i;

always @(posedge writemem) mem[address] = data; always wait (clear == 0)

Verilog-XL Modeling Style Guide

Modeling Your Hardware (Behavior-Level)

1.Declare a named event with the event keyword. The clear_mem named event is declared for this design.

2.Trigger a named event with the -> construct. Whenever the clear line is asserted, the clear_mem named event is triggered. The clear_mem event remains asserted until clear is deasserted.

3.Use an event control expression (@) to control statements that execute only when the named event is triggered. Note that control expressions can reference named events declared and triggered in other modules. Specify the full hierarchical name of the named event. When clear_mem is triggered, the entire memory is initialized to 0.

Overriding Procedural Assignments on Registers

You can override a procedural assignment (=) on a register by placing a continuous assignment on the register for a controlled period of time. Use the assign keyword to begin a continuous assignment, and the deassign keyword to end a continuous assignment. The force and release statements perform similar functions, but are meant primarily to assist in debugging.

The following example shows how you use continuous assignments on a register to override a procedural assignment. “See Step n” comments in the example correspond to descriptive steps that follow the example.

Example: Overriding procedural assignments on registers

else if (!preset) assign q = 1;

else

deassign q; // See Step 3 endmodule // DFF

Verilog-XL Modeling Style Guide

Modeling Your Hardware (Behavior-Level)

1.You typically assign values to a register with a procedural assignment (=). On the positive edge of the clock, the output q takes on the value of the input d.

2.Begin a continuous assignment on a register with the assign keyword. Whenever clear transitions to 0 (clear asserted) or preset transitions to 0 (preset asserted), a continuous assignment forces q to 0 or 1, respectively, regardless of the previous procedural assignment.

3.End the continuous assignment with the deassign keyword. The procedural assignment to q resumes. When clear and preset are deasserted, the continuous assignment on q ends.