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Verilog-XL Modeling Style Guide

Modeling Your Hardware

2.Define macros with ‘define to save typing source code that is repeated frequently in your model.

Stimulus is applied to the data signal 16 (4’b) times, so defining the stim macro saves typing. Note that the macro definition for stim references the period macro.

3.Use macros by placing a backward tick ( ) before the macro name.

In this case, the clock cycle is defined to be half the clock period, which is defined by the period macro.

Resetting Compiler Directives

Use the ‘resetall compiler directive to reinstate the default values of all directives. Unless you reset them, the effects of compiler directives carry over from module to module. You can specify ‘resetall anywhere in a module. However it is considered good coding practice to reset compiler directives at the beginning of each source file, followed by any directives you want to set in your file.

Note: The ‘resetall compiler directive does not reset text macros.

The following example shows how the ‘resetall compiler directive returns the current set of compiler directives to their default values. “See Step n” comments in the example correspond to descriptive steps that follow the example.

Example: Resetting compiler directives

‘default_nettype wand

// See Step 1

module file1;




endmodule // file1



// See Step 2

‘default_nettype wire

// See Step 3

module file2;




endmodule // file2


1.Use compiler directives for your module as needed. The file1 module is affected by the ‘default_nettype directive, which declares the default net type as wand.

2.Reset active compiler directives with the ‘resetall compiler directive.

None of the compiler directives defined prior to the file2 module definition affect file2. It is good practice to have a ‘resetall directive at the beginning of each module, particularly when the module is in a separate file, to avoid having compiler directives from other modules inadvertently affect a module.

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Product Version 3.2

Verilog-XL Modeling Style Guide

Modeling Your Hardware

3.After ‘resetall, specify any compiler directives you want to be active. The default nettype for module file2 is wire.

Declaring Nets

You can declare the physical connections between structural entities (such as gates) by declaring nets. The simplest type of net is a wire (wire, tri), but Verilog-XL supports more complex nets: wired logic (wand, wor, triand, trior), resistive pull to a supply (tri0, tri1), supply connections (supply0, supply1), and tri-state nets (trireg, which models charge storage nodes). Only trireg nets can store values. All other nets do not store values.

The following example shows the declaration of several types of nets: wire, tri, and wand. “See Step n” comments in the example correspond to descriptive steps that follow the example.

Example: Declaring nets

module net_declarations(in1, in2);


input in1, in2;

// See Step 1

wire a;

tri #2 [3:0] b;

// See Step 2

wand c;

not (c, in1);

// See Step 3

not (c, in2);




endmodule // net_declarations


1.Net a is a simple wire declaration, while net b is a 4-bit tri declaration with a wire delay of 2. The wire or tri declarations have identical syntax and function. Use wire for nets that are driven by a single gate or a continuous assignment. Use tri where multiple drivers drive a net.

2.The c net is a wired AND. Declare wired-AND nets with the wand keyword. A wired AND differs from an AND gate only in that wired ANDs propagate Z values, while gates convert Z values to X.

3.The c net is used as the output of two inverters. Because c is a wired AND, c is 1 only when both in1 and in2 are 0.

Assigning Values to Nets (Continuous Assignments)

You can model combinational logic without specifying gates by using a continuous assignment statement. Verilog-XL updates the value of the net every time a change occurs to the right-hand side of the assignment statement. Continuous assignment statements

January 2001


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// See Step 1 // See Step 2

Verilog-XL Modeling Style Guide

Modeling Your Hardware

cannot go in procedural blocks (initial, always). You can use conditional operators (?:) within continuous assignments.

The following example shows how continuous assignments can be used to model a busselect device. “See Step n” comments in the example correspond to descriptive steps that follow the example.

Example: Assigning values to nets

module select_bus(busout, bus0, bus1, bus2, bus3, enable, select); parameter size=8;

parameter Zee = 8’bz; output [size-1:0] busout;

input [size-1:0] bus0, bus1, bus2, bus3; input enable;

input [1:0] select; tri [size-1:0] data;

tri [size-1:0] busout = enable ? data : Zee;


data = (select == 2’b00) ? bus0 : Zee, data = (select == 2’b01) ? bus1 : Zee, data = (select == 2’b02) ? bus2 : Zee, data = (select == 2’b03) ? bus3 : Zee;

endmodule // select_bus

1.Define a continuous assignment when you declare a net by following the net name with an assignment operator (=) followed by an expression. Because you declare a net only once, you can only make a single continuous assignment to the net. Note that all righthand side expression value changes for a given time cycle propagate to the net.

The busout output has a conditional continuous assignment; when enable is asserted,

Verilog-XL assigns data to busout, otherwise the output is all Zs.

2.Use the assign keyword to define continuous assignment statements that are not part of a net declaration. With assign, you can have any number of continuous assignments to the same net. Continuous assign statements cannot appear in procedural blocks, but the right-hand side can be any expression, including function calls.

Based on the value of select, Verilog-XL continuously assigns one of the four input buses to the data bus because the final value of the right-hand side expression for a given time cycle propagates to the net.

Declaring Registers

A register stores a value from one procedural assignment (=) to the next. You can model storage elements, or “registers,” with a reg declaration. Verilog-XL treats both positive and negative values as unsigned (positive) values. You can declare multibit registers as vectors, or as arrays of registers, which are useful for modeling memories.

January 2001


Product Version 3.2

Verilog-XL Modeling Style Guide

Modeling Your Hardware

The following example shows register declarations, including a memory declaration and assignments to the registers.“See Step n” comments in the example correspond to descriptive steps that follow the example.

Example: Declaring registers

module register_declarations;

// See Step 1

reg data1,



[7:0] address;

// See





mem [255:0];

// See



integer i;

initial begin

data1 = 1; // See Step 4 data2 = 1’b1;

address = 8’bz;

for (i=0; i<256; i = i + 1) mem[i] = 0;



endmodule // register_declarations

1.To declare registers, specify the reg keyword followed by one or more comma-separated register names. By default (without vector or array expressions), Verilog-XL declares single-bit registers. The data1 and data2 signals are declared as single-bit registers.

2.To declare multibit registers, specify the reg keyword followed by a vector expression ([most-significant bit:least-significant bit]), and then one or more comma-separated register names.

The address signal is declared as an 8-bit register.

3.You can define memories by declaring arrays of single or multibit registers. The array syntax is similar to the vector syntax, except that the array depth follows the register names.

The mem memory is a 256 element array of 16-bit registers (256x16 memory).

4.Assignments to registers are procedural assignments—they must occur in initial, always, function, or task procedures. You can assign all bits of register vectors with one assignment (note the assignment of Z to address), but you cannot operate on an entire array (note the use of a for loop to initialize the memory).

Declaring and Using Integers

You can use registers (reg) for general purposes such as counters. However, you can use the integer keyword for manipulating quantities that

January 2001


Product Version 3.2

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