Verilog-XL Modeling Style Guide

Modeling Your Hardware

Verilog-XL does not regard as hardware registers. Integers are convenient and help to distinguish between hardware registers and other quantities. Integers have a size of 32 bits.

The following example shows a common use for an integer variable: a counter for loop control. “See Step n” comments in the example correspond to descriptive steps that follow the example.

Example: Declaring and using integers

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1.To declare integers, specify the integer keyword followed by one or more variable names separated by commas. This declaration defines the integer i.

2.You can use integers in expressions. The for loop, which initializes a memory, uses the integer i as the loop counter.

3.Use %d (decimal), %h (hex), %o (octal ), or %b (binary) in formatted-output tasks (such as $display) to display integer values.

4.Use integers to index arrays and vectors.

Declaring and Using Reals

With the real keyword, you can specify and display real numbers in either decimal or scientific notation (decimal format must have at least one digit on each side of the decimal point).

The real type behaves similarly to the integer and time types. However, not all Verilog HDL operators work on real numbers, ranges are not allowed, and real number variables default to an initial value of 0.

The example shows how you declare and display real values, and how you can convert real numbers to integers. “See Step n” comments in the example correspond to descriptive steps that follow the example.

Example: Declaring and using reals

1.To declare reals, specify the real keyword followed by one or more variable names separated by commas.

2.Use %f (decimal format), %e (exponential format), or %g (whichever format is shorter) in formatted-output tasks (such as $display) to display real values.

3.Assign values to reals by specifying either decimal or exponential formats. If you specify a decimal point, you must include at least one digit on each side. For exponential format, you can specify either e or E.

4.When you assign a real to an integer, Verilog-XL rounds to the nearest integer. If you want to truncate the real value, use $rtoi. You can assign an integer to a real directly, or with $itor. In both cases, Verilog-XL converts Z and X integer values to a real value of 0.

5.Use real values as you would integer or time values. Note, however, that not all operators work on real values (for example, concatenation).

The delay specification has a delay value of 1.2.

6.Note that uninitialized reals default to 0 whereas integers default to X.

Declaring and Using Strings

Strings are a series of characters, each represented by an 8-bit ASCII code. Verilog HDL operators manipulate strings as though they were a single numerical value. You can store string variables in registers (reg) and make assignments by specifying a string surrounded by quotation marks (" "), or by specifying the ASCII codes.

Verilog-XL Modeling Style Guide

Modeling Your Hardware

The example shows how you declare string variables and how the concatenation operator concatenates strings. “See Step n” comments in the example correspond to descriptive steps that follow the example.

Example: Declaring and using strings

1.Specify the reg keyword with a string name variable to declare strings. The stringvar variable can store up to 14 ASCII characters. The register must have 8 bits for every character in the string that the variable stores.

2.Assign values to a string variable by specifying the string in quotation marks (" "). You can also assign the ASCII code to the variable instead of specifying the string itself.

3.Display string variables with the %s format specifier.

4.All Verilog HDL operators can manipulate string variables. The operators treat string operands as a single numerical value. The concatenation operator adds three exclamation points to stringvar.

5.The output shows the ASCII code for the Hello world string. The string Hello world is assigned to stringvar.

Declaring Vectors

You can create vectors—buses and multibit registers—by specifying bit ranges when you declare nets and registers (not time or integer types). Specify vectors by preceding the name of the net or register variable with a range specification. You can reference a vector as a single entity or as a group of scalars (single-bit values). Both array and memory declarations are closely related to vector declarations.

Verilog-XL Modeling Style Guide

Modeling Your Hardware

The example shows how you declare a 4-bit register using four instances of a flip-flop, where some of the input and output signals of the 4-bit register are vectors. “See Step n” comments in the example correspond to descriptive steps that follow the example.

Example: Declaring vectors

endmodule // hardreg

1.When you do not explicitly declare a vector, the result is a scalar variable—a single bit entity.

Both clk and clrb are single-bit inputs.

2.Vector declarations appear between the data type name and variable name, and take the form [most-significant bit:least-significant bit].

The hardreg module defines a 4-bit register, and therefore has a 4-bit input (d) and a 4-bit output (q).

3.Access the individual bits of a vector by following the vector name with a bit index: vector_name[index_expr]. Note that unlike arrays, you can operate on the entire vector as a single entity by using just the vector name.

Each input to and output from each flop instance is a single bit of the hardreg vectors d and q.

Declaring Arrays

You can use an array to declare multiple registers (reg, time, and integer). To specify an array, specify the variable name of a net or register followed by an array index declaration.

You can operate only on individual elements of the array. Verilog HDL does not support multidimensional arrays. Arrays are closely related to vectors. A common use of arrays is to create memories.

The example shows how an array of time variables can be used to store the simulation times when a task is called. “See Step n” comments in the example correspond to descriptive steps that follow the example.