ABOUT THIS MANUAL
1.4RELATED LITERATURE
Literature related to IA-32 processors is listed on-line at this link: http://developer.intel.com/design/processor/
Some of the documents listed at this web site can be viewed on-line; others can be ordered. The literature available is listed by Intel® processor and then by the following literature types: applications notes, data sheets, manuals, papers, and specification updates.
See also:
•The data sheet for a particular Intel IA-32 processor
•The specification update for a particular Intel IA-32 processor
•AP-485, Intel Processor Identification and the CPUID Instruction, Order Number 241618
•IA-32 Intel® Architecture Optimization Reference Manual, Order Number 248966
Vol. 2A 1-7
ABOUT THIS MANUAL
1-8 Vol. 2A
2
Instruction Format
CHAPTER 2
INSTRUCTION FORMAT
This chapter describes the instruction format for all IA-32 processors. The instruction format for protected mode, real-address mode and virtual-8086 mode is described in Section 2.1. Increments provided for IA-32e mode and its sub-modes are described in Section 2.2
2.1INSTRUCTION FORMAT FOR PROTECTED MODE, REALADDRESS MODE, AND VIRTUAL-8086 MODE
IA-32 instruction encodings are subsets of the format shown in Figure 2-1. Instructions consist of optional instruction prefixes (in any order), primary opcode bytes (up to three bytes), an addressing-form specifier (if required) consisting of the ModR/M byte and sometimes the SIB (Scale-Index-Base) byte, a displacement (if required), and an immediate data field (if required).
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Instruction |
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Opcode |
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ModR/M |
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SIB |
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Displacement |
Immediate |
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Prefixes |
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Up to four |
1-, 2-, or 3-byte |
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1 byte |
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1 byte |
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Address |
Immediate |
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prefixes of |
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opcode |
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(if required) |
(if required) |
displacement |
data of |
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1 byte each |
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of 1, 2, or 4 |
1, 2, or 4 |
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(optional) |
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bytes or none |
bytes or none |
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7 |
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6 5 |
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3 2 |
0 |
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7 |
6 5 |
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3 2 |
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Mod |
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Reg/ |
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R/M |
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Scale |
Index |
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Base |
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Opcode |
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Figure 2-1. IA-32 Instruction Format
Vol. 2A 2-1