INSTRUCTION SET REFERENCE, A-M
HADDPS: Packed Single-FP Horizontal Add
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64-Bit |
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Opcode |
Instruction |
Mode |
Leg Mode |
Description |
F2 0F 7C /r HADDPS xmm1, |
Valid |
Valid |
Horizontal add packed single- |
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xmm2/m128 |
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precision floating-point values from |
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xmm2/m128 to xmm1. |
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Description
Adds the single-precision floating-point values in the first and second dwords of the destination operand and stores the result in the first dword of the destination operand.
Adds single-precision floating-point values in the third and fourth dword of the destination operand and stores the result in the second dword of the destination operand.
Adds single-precision floating-point values in the first and second dword of the source operand and stores the result in the third dword of the destination operand.
Adds single-precision floating-point values in the third and fourth dword of the source operand and stores the result in the fourth dword of the destination operand. See Figure 3-11.
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+$''36 [PP [PP P |
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[PP |
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5(68/7 |
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Figure 3-11. HADDPS: Packed Single-FP Horizontal Add
3-426 Vol. 2A |
HADDPS: Packed Single-FP Horizontal Add |
INSTRUCTION SET REFERENCE, A-M
In 64-bit mode, use of the REX.R prefix permits this instruction to access additional registers (XMM8-XMM15).
Operation
xmm1[31:0] = xmm1[31:0] + xmm1[63:32]; xmm1[63:32] = xmm1[95:64] + xmm1[127:96]; xmm1[95:64] = xmm2/m128[31:0] + xmm2/m128[63:32];
xmm1[127:96] = xmm2/m128[95:64] + xmm2/m128[127:96];
Intel C/C++ Compiler Intrinsic Equivalent
HADDPS __m128 _mm_hadd_ps(__m128 a, __m128 b)
Exceptions
When the source operand is a memory operand, the operand must be aligned on a 16-byte boundary or a general-protection exception (#GP) will be generated.
Numeric Exceptions
Overflow, Underflow, Invalid, Precision, Denormal.
Protected Mode Exceptions
#GP(0) |
For an illegal memory operand effective address in the CS, DS, ES, FS or |
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GS segments. |
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If a memory operand is not aligned on a 16-byte boundary, regardless of |
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segment. |
#SS(0) |
For an illegal address in the SS segment. |
#PF(fault-code) |
For a page fault. |
#NM |
If CR0.TS[bit 3] = 1. |
#XM |
For an unmasked Streaming SIMD Extensions numeric exception |
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(CR4.OSXMMEXCPT[bit 10] = 1). |
#UD |
If CR0.EM[bit 2] = 1. |
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For an unmasked Streaming SIMD Extensions numeric exception |
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(CR4.OSXMMEXCPT[bit 10] = 0). |
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If CR4.OSFXSR[bit 9] = 0. |
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If CPUID.01H:ECX.SSE3[bit 0] = 0. |
HADDPS: Packed Single-FP Horizontal Add |
Vol. 2A 3-427 |
INSTRUCTION SET REFERENCE, A-M
Real Address Mode Exceptions
GP(0) |
If any part of the operand would lie outside of the effective address space |
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from 0 to 0FFFFH. |
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If a memory operand is not aligned on a 16-byte boundary, regardless of |
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segment. |
#NM |
If CR0.TS[bit 3] = 1. |
#XM |
For an unmasked Streaming SIMD Extensions numeric exception |
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(CR4.OSXMMEXCPT[bit 10] = 1). |
#UD |
If CR0.EM[bit 2] = 1. |
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For an unmasked Streaming SIMD Extensions numeric exception |
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(CR4.OSXMMEXCPT[bit 10] = 0). |
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If CR4.OSFXSR[bit 9] = 0. |
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If CPUID.01H:ECX.SSE3[bit 0] = 0. |
Virtual 8086 Mode Exceptions |
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GP(0) |
If any part of the operand would lie outside of the effective address space |
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from 0 to 0FFFFH. |
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If a memory operand is not aligned on a 16-byte boundary, regardless of |
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segment. |
#NM |
If CR0.TS[bit 3] = 1. |
#XM |
For an unmasked Streaming SIMD Extensions numeric exception |
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(CR4.OSXMMEXCPT[bit 10] = 1). |
#UD |
If CR0.EM[bit 2] = 1. |
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For an unmasked Streaming SIMD Extensions numeric exception |
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(CR4.OSXMMEXCPT[bit 10] = 0). |
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If CR4.OSFXSR[bit 9] = 0. |
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If CPUID.01H:ECX.SSE3[bit 0] = 0. |
#PF(fault-code) |
For a page fault. |
Compatibility Mode Exceptions
Same exceptions as in Protected Mode.
64-Bit Mode Exceptions
#SS(0) |
If a memory address referencing the SS segment is in a non-canonical |
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form. |
3-428 Vol. 2A |
HADDPS: Packed Single-FP Horizontal Add |
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INSTRUCTION SET REFERENCE, A-M |
#GP(0) |
If the memory address is in a non-canonical form. |
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If memory operand is not aligned on a 16-byte boundary, regardless of |
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segment. |
#PF(fault-code) |
For a page fault. |
#NM |
If CR0.TS[bit 3] = 1. |
#XM |
If an unmasked SIMD floating-point exception and CR4.OSXM- |
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MEXCPT[bit 10] = 1. |
#UD |
If an unmasked SIMD floating-point exception and CR4.OSXM- |
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MEXCPT[bit 10] = 0. |
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If CR0.EM[bit 2] = 1. |
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If CR4.OSFXSR[bit 9] = 0. |
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If CPUID feature flag SSE3 is 0. |
HADDPS: Packed Single-FP Horizontal Add |
Vol. 2A 3-429 |
INSTRUCTION SET REFERENCE, A-M
HLT—Halt
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64-Bit |
Compat/ |
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Opcode |
Instruction |
Mode |
Leg Mode |
Description |
F4 |
HLT |
Valid |
Valid |
Halt |
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Description
Stops instruction execution and places the processor in a HALT state. An enabled interrupt (including NMI and SMI), a debug exception, the BINIT# signal, the INIT# signal, or the RESET# signal will resume execution. If an interrupt (including NMI) is used to resume execution after a HLT instruction, the saved instruction pointer (CS:EIP) points to the instruction following the HLT instruction.
When a HLT instruction is executed on an IA-32 processor supporting Hyper-Threading Technology, only the logical processor that executes the instruction is halted. The other logical processors in the physical processor remain active, unless they are each individually halted by executing a HLT instruction.
The HLT instruction is a privileged instruction. When the processor is running in protected or virtual-8086 mode, the privilege level of a program or procedure must be 0 to execute the HLT instruction.
This instruction’s operation is the same in non-64-bit modes and 64-bit mode.
Operation
Enter Halt state;
Flags Affected
None.
Protected Mode Exceptions
#GP(0) |
If the current privilege level is not 0. |
Real-Address Mode Exceptions
None.
Virtual-8086 Mode Exceptions
Same exceptions as in Protected Mode.
3-430 Vol. 2A |
HLT—Halt |
INSTRUCTION SET REFERENCE, A-M
Compatibility Mode Exceptions
Same exceptions as in Protected Mode.
64-Bit Mode Exceptions
Same exceptions as in Protected Mode.
HLT—Halt |
Vol. 2A 3-431 |