Programmable logic array (pal)

PALs are the principal representatives of programmable logic devices (PLDs). They are available in a wide range of variants, all of which are based on the principle shown in Fig. 3.39b. The differences are in the imple­mentation of the OR operations at the output. The most commonly used variants are listed in Fig. 3.42. Each different type is designated by the relevant letter shown.

The high (H) output represents the basic type shown in Fig. 3.39. In the case of the low (L) type, the output is negated. The C output is complementary. In the programmable (P) type, the user can define whether the output function or its inversion is true. For this purpose the exclusive-OR output gate is used, whose second input can be made 0 or 1 by the programming. The user has then the freedom to form the negated function and thereby utilize the PAL more efficiently if necessary. In the case of the EXOR (X) output, there is likewise an exclusive-OR gate at the output; however, it is controlled by two OR operations. This variant is used for simple implementation of adders.

The sharing (S) output has features in common with the PLAs. Here the OR matrix is also partly programmable: two adjacent OR gates can share the AND operations available to them. This makes it possible to form functions for which the number of OR gates would otherwise be insufficient.

With many PALs, an output can also be used as an input or programmed as a bidirectional port (I/O). This is the purpose of the tristate gate at the output, whose ENABLE is itself a logic function.

An important application of PALs is in sequential logic systems. In order to obviate the need for additional chips, the required registers (R) are incorporated in the PALs. They have a common clock terminal to enable construction of synchronous systems. In addition, the output signals are generally fed back internally to the AND matrix, thereby eliminating external feedback circuitry and saving on pins.

Fig. 3.41 - Implementation of the functions of Fig. 3.40 using a PLA, PAL and PROM.

Fig.3.42 - Output circuit of PAL.

PALs are also available which are designed for implementing asynchronous sequential logic systems. They allow the clock for each register to be defined by an additional logic function (AR in Fig. 3.42). In addition, these PALs usually have a freely definable set and reset function. Similar to the synchronous type, they may have internal feedback features.

Using the optimum PAL for each application would require a large number of different types - as Fig. 3.42 shows. In order to reduce the variety of types, PALs with a programmable output structure are becoming increasingly com­mon. One such variable "macrocell" (V) is also shown in Fig. 3.42. It is built around a multiplexer which can be used to select any of four different operating modes. These are defined by programming the function bits f₀ and f₁. The different operating modes are listed in Fig. 3.43. Bit f₀ determines whether or not the output is negated. Bit f₁ switches between combinatorial and registered mode. It also determines, via a second multiplexer, whether feedback is taken from the output or from the register. We can see that most PALs can be implemented in this way using a single type.

f1	f0	Type	Output	Feedback
0	0	H	Function	Output
0	1	L	Function, negated	Output
1	0	R	Register	Register
1	1	R	Register, negated	Register

Fig. 3.43 - Operating modes of the variable macrocell.

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