2.5 Counters
Counters are an important group of sequential logic systems. A counter may be any circuit, which, within certain limits, has a defined relationship between the number of input pulses and the state of the output variables. As each output variable can have only two values, for n outputs, there are 2" possible output combinations, although often only some of these are used. It is
Fig. 2.40 - State table of a Fig. 2.41 - Output states of a straight binary
straight binary counter. up-counter as a function of time.
unimportant which number is assigned to which combination, but it is useful to choose a representation which can subsequently be easily processed. The simplest circuits are obtained for the straight binary notation.
Figure 2.40 shows the relationship between the number, Z, of input pulses and the values of output variables z,-, for a 4-bit straight binary counter. If this table is read from top to bottom, two patterns emerge:
1) an output variable zt always changes state when the next lower value Zj -1 changes from 1 to 0.
2) an output variable z; always changes state when all lower variables z,-_!,..., z0 have the value 1 and a new pulse arrives.
These patterns can also be seen in the timing diagram in Fig. 2.41. Pattern (1) is the basis of an asynchronous counter (ripple gounter), whereas pattern (2) yields the synchronous counter.
Occasionally, counters are required, whose output state is reduced by 1 for each count pulse. The operational principle of such a down-counter can also be inferred from the table in Fig. 2.40 by reading it from the bottom up. It follows that
la) an output variable z; of a down-counter changes state whenever the next lower variable z,--! changes from 0 to 1.
2a) an output variable z, of a down-counter always changes state when all
lower variables zt _,,..., z0 have the value 0 and a new clock pulse
arrives.
Asynchronous straight binary counter
A straight binary asynchronous (ripple) counter can be implemented by arranging flip-flops in a chain, as in Fig. 2.42, and by connecting each clock input C to the output Q of the previous flip-flop. If the circuit is to be an up-counter, the flip-flops must change their output states when their clock inputs C change from 1 to 0. Edge-triggered flip-flops are therefore required, e.g. JK master-slave flip-flops where J = K = 1. The counter may be extended to any size. Using this principle, one can count up to 1023 with only 10 flip-flops.
Fig. 2.42 - Asynchronous straight binary counter CLK = Clock RCO = Ripple Carry Output
Flip-flops triggered by the positive-going edge of the clock pulse can also be employed, e.g. single-edge triggered D flip-flops. If they are connected in the same way as in Fig. 2.42, down-counter operation is obtained. For up-counter operation, their clock pulse must be inverted. This is achieved by connecting each clock input to the Q-output of the previous flip-flop.
Every counter is also a frequency divider. The frequency at the output of flip-flop F0 is half the counter frequency. A quarter of the input frequency appears at the output of Fj, an eighth at the output of F2, etc. This property of frequency division can be seen clearly in Fig. 2.41.
