- •1 Combination Circuits
- •1.1 Circuitry ttl-elements with Shottky diodes
- •Levels of Integration
- •Typical Set of ttl iCs
- •Transistor-transistor logic (ttl)
- •1.2 Element with the open collector Open-collector outputs
- •Tristate outputs
- •1.3 Emitter-coupled logic (ecl)
- •Emitter-coupled multivibrator
- •Emitter-coupled Schmitt trigger
- •1.4 Decoder
- •Priority decoder
- •Binary Decoders
- •Decoder Networks
- •1.5 Coder units Encoder Networks
- •Binary Encoders
- •Priority Encoders
- •1.6 Multiplexers (Selectors)
- •1.7 Multiplexer Trees
- •Demultiplexer Networks
- •Encoder Networks
- •1.8 Demultiplexers (Distributors)
- •1.9 Applicanion of multiplexer
- •1.10 Code converters
- •1.11 Shifters
- •Shifter Networks
- •Barrel Shifter
- •1.12 Comparators
- •Window comparator
- •Digital comparators
- •2 Sequentional Circuits
- •2.1 Circuritry of flips
- •Sequential logic systems
- •Integrated flip-flops
- •Transparent flip-flops
- •Clocked rs flip-flop
- •Clocked d flip-flop
- •Flip-flops with intermediate storage
- •2.2 Flips types Single-edge-triggered flip-flops
- •2.3 Statik registers
- •2.4 Shift register Combinatorial shift register (barrel shifter)
- •Shift Registers
- •2.5 Counters
- •Asynchronous straight binary counter
- •Counters
- •Ripple Counters
- •Asynchronous bcd counter
- •2.6 Synchronous reversal counters
- •Synchronous straight binary counters
- •Synchronous bcd counter
- •Synchronous one-shot
- •Synchronous edge detector
- •Synchronous clock switch
- •2.7 Schmitt flip-flops Schmitt trigger
- •Inverting Schmitt trigger
- •Precision Schmitt trigger
- •3 Memory Devices
- •3.1 Circuitri of memori element Semiconductor memories
- •3.2 Mask-type lic of the rom
- •RaMs as shift registers
- •First-In-First-Out Memories (fifOs)
- •Fifo implementation using standard raMs
- •Error detection and correction
- •Parity bit
- •Hamming code
- •3.3 Rom with singl programming Read-only memories (roMs)
- •Mask-programmed roMs (mroMs)
- •Programmable roMs (proMs)
- •3.4 Memori element with electrical erase Electrically erasable proMs (eeproMs)
- •3.5 Static ram
- •Timing considerations
- •3.6 Dynamic raMs
- •Dynamic ram controllers
- •3.7 Devices programmed
- •Programmable logic array (pal)
3.2 Mask-type lic of the rom
Two-port memories
Two-port memories are special RAMs which allow two independent processes to access common data. This enables data to be exchanged between the two processes [3.4, 3.5]. To be able to do this, the 2-port memory must have two separate sets of address, data and control lines, as shown in Fig. 3.3. Implementation of this principle is subject to limitations, since it is basically impossible to write into the same memory cell simultaneously from both ports.
Fig. 3.3 - External connections of a 2-port memory.
The "Read-While-Write" memories overcome this problem by only reading from one of the two ports and only writing at the other. Figure 3.4 shows that memories of this type have two separate address decoders which allow simultaneous writing to one address while reading from another.
If reading and writing are to take place at both ports of a two-port memory an access conflict can generally only be avoided by preventing simultaneous memory access. To do this, the address, data and control lines can be made available via multiplexers to the port accessed as shown in Fig. 3.5. In many cases, the two processes accessing the memory are synchronized to prevent simultaneous access. If this is not possible, a priority decoder (arbiter) can be used which, in the event of access overlap, temporarily stops one of the two processes by a wait signal. Some integrated 2-port memories are listed in Fig. 3.6. Their capacities, however, are limited. In order to implement large two-port memories, it is advisable to use normal RAMs in conjunction with a dual-port RAM controller. In this case the Valvo 74LS764 offers particular advantages, since it supports the operation of dynamic RAMs as two-port memories.
Fig. 3.4 - Structure of a Read-While-Write memory with separate address inputs.
Fig. 3.5 - Two-port memory with standard RAMs.
Capacity |
Organization |
Type |
Manufacturer |
Operating power, typical |
Access time, max |
Pins |
8 kbit
|
1k x 8
|
IDT7130
|
Id, Cy, Am
|
325 mW
|
35ns
|
48
|
16 kbit
|
2k x 8
|
1DT7132
|
Id, Cy, Vt
|
325 mW
|
35ns
|
48
|
32 kbit
|
4k x 8
|
IDT7134
|
Id
|
500 mW
|
35ns
|
48
|
32 kbit
|
2k x 16
|
IDT7133
|
Id
|
375 mW
|
45ns
|
68
|
64 kbit
|
8k x 8
|
IDT7005
|
Id
|
750 mW
|
35ns
|
68
|
64 kbit
|
4k x 16
|
IDT7024
|
Id
|
750 mW
|
30ns
|
84
|
128 kbit
|
16k x 8
|
IDT7006
|
Id
|
750 mW
|
35ns
|
68
|
128 kbit
|
8k x 16
|
IDT7025
|
Id
|
750 mW
|
30ns
|
84
|
Manufacturers: Am = AMD, Cy = Cypress, Id = IDT, Vt = VTI
Fig. 3.6 - Examples of two-port memories (CMOS).
