Sequential logic systems
A sequential logic system is an arrangement of digital circuits which can carry out logic operations and, in addition, store the states of individual variables. It diners from a combinatorial logic system in that the output variables yj are not only dependent on the input variable xi, but also on the previous history which is represented by the state of flip-flops.
In the following we shall first discuss the design and operation of integrated flip-flops.
Integrated flip-flops
We shall now demonstrate the operation of flip-flops with reference to gates. This approach defines their basic operation irrespective of the particular technology employed.
Transparent flip-flops
By connecting two NOR
gates in a feedback arrangement as
in Fig. 2.3,
we obtain a flip-flop which has complementary outputs Q and
and two inputs S (Set) and R (Reset).
If the complementary input state S = 1 and R = 0 is applied, we have
and
The two outputs, therefore, assume complementary states. Similarly, for R = 1 and S = 0, the opposite output state is obtained. If we make R = S = 0, the old output state is retained. This explains why RS flip-flops are used as memories. When R = S = 1, the two outputs become simultaneously 0; however, the output state is no longer defined when R and S then become simultaneously 0. Consequently, the input state R = S = 1 is generally disallowed. The switching states are summarized in the truth table in Fig. 2.4, with which we are already familiar from the transistor circuit
In Section 9.2 we showed that a logic
equation does not change if all the variables are negated and the
arithmetic operations (+) and (•) are interchanged. Applying
this rule here, we arrive at the RS flip-flop comprising NAND
gates shown in Fig.
2.5, which has the same truth table as
that shown in Fig. 2.4.
However, note that the input variables are now
and
.
As we shall be frequently using the RS flip-flop comprising NAND
gates, we have given its truth table
for input variables
and
in Fig. 2.6.
Fig. 2.3 - RS flip-flop comprising NOR gates. . Fig. 2.4 - Truth table for an RS flip-flop.
Fig. 2.5 - RS flip-flop comprising NAND gates Fig. 2.6 .- Truth table for an RS flip- flop comprising NAND gates.
Clocked rs flip-flop
We frequently require an RS flip-flop which only reacts to the input state at a specific point in time. This time is determined by an additional clock variable C. Figure 2.7 shows a statically clocked RS flip-flop of this kind. If C = 0, then = = l. In this case the flip-flop stores the old state. For C = 1, we get
R = R' and S = S'.
The flip-flop then behaves like a normal RS flip-flop.
Fig. 2.7 - Statically clocked RS flip-flop.
Clocked d flip-flop
We shall now examine how the value of a logic
variable D can be stored using the flip-flop in Fig.
2.7. We have seen that Q = S if
complementary input states are applied and C = 1. In order to store
the value of a variable D, we therefore need only make S = D and R =
.
The inverter G5
in Fig. 2.8
is used for this purpose. In the resulting data latch, Q = D as long
as clock C = 1. This may also be seen from the truth table in Fig.
2.9. Due to this property, the clocked
data latch is also known as a transparent D flip-flop. If we make C =
0 the existing output state is stored.
Fig. 2.8 - Transparent D flip-flop (D latch). Fig. 2.9 - Truth table for the transparent
D-flip-flop.
Fig.2.10 - Practical implementation of a Fig. 2.11 - Circuit symbol for a transparent transparent D flip-flop. D flip-flop.
We can see that NAND gate G4 in Fig. 2.8 acts as an inverter for D when C = 1. Inverter G5 can therefore be omitted, producing the practical implementation of a D latch shown in Fig. 2.10 the circuit symbol is given in Fig. 2.11.
IC types:
74LS75 (TTL); 10133 (ECL); 4042 (CMOS)