Fifo implementation using standard raMs
For implementation of large FIFOs it is advisable to use standard RAMs, thereby providing the maximum degree of integration. This involves replacing tie read-while-write memory in Fig. 3.11 by a two-port memory implemented ling standard RAMs as shown in Fig. 3.5. The resultant configuration is shown in Fig. 3.13.
Fig. 3.13 - FIFO implementation with standard RAMs.
Since it is not possible to read and write simultaneously with a normal RAM, these operations must be performed sequentially. Coordination is provided by an "arbiter" in the control logic. If data are to be entered while a read-out is in progress, the read cycle is first completed and the input delayed via a "wait" signal, and vice versa if an output is to take place while an input is in progress. The cycle that was first requested is executed first in each case. If the read and write clock pulses coincide, the arbiter makes a random decision. Owing to the possible "wait" delay, the access time can double under worst-case conditions. The control logic required to operate a RAM as a FIFO can be obtained in the form of an integrated circuit known as a FIFO RAM controller:
512 ... 64k words, 10 MHz, TTL: 674219, MMI
512 ... 64k words, 15 MHz, CMOS: ISP9119, Intersil
256 ... 16k words, 60 MHz, ECL: HXA241-141, Valvo (RTC)
Error detection and correction
When data are stored in RAMs, two different types of error can occur: permanent and transient errors. The permanent errors (hard errors) are caused by faults in the ICs themselves or in the associated controller circuits. The transient errors (soft errors) only occur randomly and are not therefore reproducible. They are mainly caused by -radiation of the package. It may not only discharge memory capacitors in dynamic RAMs but also cause flip-flops in static RAMs to change state. Transient errors can also result from noise pulses generated inside or outside the circuit [3.7].
The occurrence of memory errors can have far-reaching consequences. Thus a single error in a computer memory might not only produce an incorrect result, but even cause the program to crash completely. Methods have therefore been developed to indicate the occurrence of errors. In order to do this, one or more check bits must be processed in addition to the actual data bits. The more check bits used, the more errors can be detected or even corrected.
Parity bit
The simplest method of error detection consists of transmitting a parity bit p. Even or odd parity can be defined. For even parity check, the parity bit added to the data word is set to zero if the number of ones in the data word is even. It is set to one if this number is odd. This means that the total number of ones transmitted in a data word including parity bits is always even, or, for odd parity, always odd.
The even parity bit can also be interpreted as the sum (modulo-2) of the data bits. This checksum can be calculated as the exclusive-OR of the data bits.
The implementation of a parity generator is shown in Fig. 3.14. The exclusive-OR gates can be in any sequence. It is chosen such that the sum of the delay times involved remains as small as possible.
For error detection purposes, the parity bit is stored together with the data bits. When the data are read out, the parity can then be regenerated as shown in Fig. 3.15 and compared with the stored parity bit by an exclusive-OR operation. If they differ, an error has occurred and the error output becomes f = 1. This allows each single-bit error to be detected. However, no correction is possible, since the bit containing the error cannot be located. If several bits contain errors, an odd number of errors can be detected, whereas an even number cannot.
Fig. 3.14 - Parity generator for even parity with 8 inputs.
IC types: 8-bit: SN 74180 (TTL); 9-bit: SN 74 S280 (TTL);
12-bit: MC 10160 (ECL); MC 14531 (CMOS)
Fig. 3.15 - Data memory with parity checking (using 8-bit data words as an example).