1.11 Shifters

A simple shifter, shown in Figure 1.54, is a combinational module that has an (n+2)-bit input x, an n-bit output y, and two 1-bit control inputs: d (for the direction of shift) and s (for shift or no-shift).

To construct networks of shifter modules, it is convenient to have the output controlled by an enable input E so that the output is 0 when E=0.

The output corresponds to the input x = (x_n, x_n-1, . . . ,x₀, x_-1) shifted one bit left, one bit right, or unchanged as specified by the d and s inputs. The shifter operation is specified as follows:

yi=	xi-1 if d= 1 and s = 1 and E= 1 (left shift)
	xi+1 if d=0 and s = 1 and E= 1 (right shift)
	xi if s=0 and E=1 (no shift)
	0 if E=0

where

Fig. 1.54 - n-Bit simple shifter. (a) Block representation, (b) ”right shift” , (с) “ lefte shifter”.

The leftmost and rightmost values are specified by means of the variables x_-1 and x_n. In left shift y₀ =x_-1 and in right shift y_n-1=x_n. Some typical cases for the values of these additional variables are

x-1=	0 left shift with 0 insert
	1 left shift with 1 insert
	xn-1 left rotate

xn=	0 right shift with 0 insert
	1 right shift with 1 insert
	x0 right rotate

A simple shifter can be implemented with gates, multiplexers, or pass-transis­tors as shown in Figure1.55.

Fig. 1.55 - Simple-shifter implementation (a) with gates, (b) with multiplexer and (c) with pass transistor.

A p-shifter is a generalization of the simple shifter in which the amount of shift can be 0,1 , . . . , p to the left or to the right (bidirectional p-shifter). The shift distance is specified by a control vector s of [log₂(p+ l)] bits and the shift direction by the input d. The input vector has n+2p bits. The subvectors ( , . . . , x_n) and (x_-1, . . . , x_-p) provide the additional bits required for the shifts (Figure 1.56.a).

Fig. 1.56 - n-Bit p-shifter. (a) Block diagram, (b) n-bit 3-shifter implementation.

A high-level description of the p-shifter module is

yi=	xi-s if d=1and E=1 (left shift)
	xi+s if d=0 and E=1(right shift)
	0 if E=0

where s is the shift distance and 0  i  n-1.

An implementation of a 3-shifter using multiplexers is shown in Figure 1.56.b.

Shifter Networks

We consider next how large shifters can be realized using the k-bit p-shifter modules described. We consider only the case of unidirectional right-shift. In what follows we assume that all shifters and shifter modules are of this unidirectional type, without explicitly saying it each time. The modifications for left and for bidirectional shift are left for Exercise 4.40.

An n-bit p-shifter can be implemented with n/k k-bit p-shifter modules as illustrated in Figure 1.57. The p least significant inputs of the (m+1)st module are the same as the p most significant inputs of the mth module. The delay of this shifter is the same as the delay of a shifter module.

Fig. 1.57 - Right p-shifter network (Sift control not shown).

A 12-bit 3-shifter, implemented by three 4-bit 3-shifter modules, is illustrated in n The mode of operation is shift right 0, 1, 2, or 3 places with 0 insert.

Fig. 1.58 - A 12-bit right 3-shifter.

An n-bit q-shifter can be implemented in several ways using k-bit p-shifter mod­ules (n > k, q >p). One such implementation is described in the following example.

Figure 1.59 shows the implementation of an 8-bit 7-shifter using 4-bit l-shifter modules and a 2-input binary decoder. The input is a = (a₇ , . . . , a₀), the output is b = (b₇, … , b₀), and the operation mode is Rotate Right 0, 1, . . . , 7 position.

The shifter network is organized as a rectangular array of shifter modules. Each row corresponds to an 8-bit 1-shifter. The first row can rotate 0 or 1 positions, the second row can rotate 2 or 3 positions, and so on, the last row rotating 6 or 7 positions. The decoder enables one of the rows, and the outputs of the rows use a wired-OR connection.

Fig. 1.59 - Array implementation of an 8-bit 8-shifter (right rotate only).