1.2.3 Basic principles of construction of cyclic сodes coders

In the beginning let’s consider the construction of the cyclic codes (n, k) coders. At their construction, as a rule, the division of the combination of the simple k-code, multiplied by х^r is used, that allows to get a separable code. The construction of coder is shown in a fig. 1.2. It has r-digits shift register (the amount of memory cells is equal to the number of check bits), three keys and two-input adders modulo 2, thus number of them is less the number of nonzero members of generator polynomial Р(х) on unit. A structure of logical feed-backs in the shift register is defined by the type of generator polynomial

P(x) = a₀ + a₁x+ a₂x² +…+ a_r-1x^r-1+ a_rx^r.

Figure 1.2 – Flow diagram of the cyclic (n, k) code coder

Adders modulo 2 (m2) are presented in a chart in the case, if corresponding coefficients is equal “1”. Adders set in the diagram before associated memory cell.

A coder works as follows. In the beginning the electronic key К2 is closed, and the electronic keys К1 and К3 are open. Informative sequence (code combination of the simple k-element code) enters simultaneously the input and to the input adder. In the process of its passing on the k-th clock cycle the binary elements of r check bits accumulate in the cells of shift register. In the (k+1)-th clock cycle the electronic keys К1 and К3 close, and the electronic key К2 opens. Written in the cells of shift register r check bits after r clock cycles enter the output of the encoder.

1.2.4 Syndrome decoding of cyclic codes

Let’s consider the decoders of cyclic codes. The construction of decoder for errors detection is shown in a fig. 1.3.

Figure 1.3 – Flow diagram of the cyclic (n, k) code decoder

The decoder has: buffer register of k-bits, decoding register, the chart of which is similar to the chart of the coder, logical charts OR, AND with the trigger, executing functions of the keys.

A decoder works as follows. The received informative sequence writes simultaneously in buffer and in decoding registers. On (k+1)-th clock cycle the electronic key &_k+1 is closed and in this case the information bits of the received code combination appear in a buffer register only. Check bits continue to enter decoding register.

On (n+1)-th clock cycle, after the reception of the last digit of code combination, the electronic key &_k+2 is open. If code combination is accepted without errors, then in the cells of decoding register only zeros will be written, and the signal "ERROR" will be absent. A presence even in one cell of decoding register of unit testifies to the errors in the received information. On the output of the chart “OR” at this case a signal "ERROR" will appear, that can be used for deleting of the accepted with errors code combination accumulated in the buffer register.

If a decoder is used in the mode of the correction of errors, then it is necessary to specify the site of the error information bits. In the structure of the decoder instead of chart “OR” include the decipherer of the syndrome, producing on its output signal "1" during fixing in the cells of decoding register of remainder different from zero. Units appear at times so in an output of the adder modulo 2 it coincided with passing of the error informative bit. Thus error bit, getting through output adder, changes its sign on inverse, i.e. correct.

For the position-fix of an error element received code combination of cyclic code use a remainder from dividing of this code combination by the generator polynomial Р(х). The got remainder R(x) is the syndrome of error. This procedure will be realized by comparison of remainder R(x) with the table of syndrome combinations formed by dividing of errors vectors e(x) by the generator polynomial Р(х).

As an example let’s consider the cyclic code decoder (15, 11) with the generator polynomial Р(х) = х⁴ + х + 1, correcting single errors. For this code a single error vector e(x) = х¹⁴ (100000000000000) is divided by the generator polynomial Р(х) = х⁴ + х + 1, forming the remainder S₁₄(x) = х³ + 1. If in the accepted combination of cyclic code the error is in 15^th position, i.e. bit х¹⁴, then a remainder from dividing of it by Р(х) will coincide with S₁₄(x).

Syndrome combinations for the errors vectors х¹³, х¹², х¹¹, х¹⁰, х⁹, х⁸, х⁷, х⁶, х⁵, х⁴, х³, х², х¹, х⁰ form similarly. For the chosen cyclic code with atomicity n = 9 have:

Table 1.2 – The syndrome table for cyclic (15,11) code

Error	Syndrome	Error	Syndrome
х14	х3 + 1	х6	х3 + х2
х13	х3 + х2 + 1	х5	х2 + х
х12	х3 + х2 + х + 1	х4	x + 1
х11	х3 + х2+ х	х3	х3
х10	х2 + х + 1	х2	х2
х9	х3 + х	х1	х1
х8	х2 + 1	х0	1
х7	х3 + х + 1

Comparing the remainder R(x) with syndrome combinations S_i(x), , get information about an error element in the accepted combination of the cyclic code.

So, the correction of errors is based on correspondence between the amount of syndromes values and the amount of the corrected errors. However at multiplicity of errors t > 1 this accordance breaks. As a rule, takes place additional input of error symbols, that is the serious defect of syndrome decoder.