Diss / 10

To determine the required memory capacity of digital signal reprocessing microprocessor subsystem, we assume that 10 false target pips are stored by the memory device in addition to the 20 true target pips. Our estimation shows that data about a single target trajectory requires approximately fifteen 32-bit words. Consequently, to store data about 30 tracked trajectories approximately four hundred and fifty 32-bit cells are required. Moreover, to store data on the detected target trajectories and the new target trajectories taking into consideration a reserved memory capacity, it is reasonable to have approximately 100 more 32-bit cells. The memory capacity requires about 400–500 cells. Thus, to solve the digital signal reprocessing problems we need about 103 memory cells.

The foregoing analysis shows the digital signal reprocessing problems do not require high computational resources compared to the previous stages of target return signal processing. This allows to assign for the digital signal reprocessing microprocessor subsystem the problems to control over all elements and parameters of the CRS and the problems of the current hardware and computational process control, additionally. Considering that the control optimization problems are not solved in dynamic mode in the automatic “radar complex–global digital signal processing complex” system and the control system is constructed as the system with a predetermined fixed sequence of control commands, we do not consider such system in the present chapter. It is assumed that the scheduled problems are considered and analyzed at the next stage of designing and construction of the CRS.

9.6  STRUCTURE OF DIGITAL SIGNAL PROCESSING SUBSYSTEM

Functional requirements, cost, reliability, conveniences in fault lookup, maintainability—all these factors are taken into consideration in the course of designing the global digital signal processing structure of the CRS. The functional requirements to individual elements of this structure, which have been discussed in the previous sections, are evidences of differences in the intensity of information flows processed by the central computer system of the radar complex. The digital coherent target return preprocessing subsystem working in real time has the greatest service load. For this reason, given the latest technological breakthroughs in signal detection and signal processing theory and in computer applications, there is a need to design and construct a specific nonprogrammable microprocessor subsystem for the digital coherent target return preprocessing subsystem working in real time, which consists of specific adders, mixers, convolution networks, memory devices based on VLSI, and charge injection devices. Without any doubts, we can state that the possibility of designing and constructing such specific microprocessor subsystems is the foundation stone to developing solutions for the problems encountered in automatic digital target return signal processing under real conditions of CRS functioning.

At the output of digital coherent target return preprocessing microprocessor subsystem the information density is essentially reduced, and at the stage of noncoherent digital signal preprocessing, we can use the programmable microprocessor subsystems. Analysis of requirements to specific subsystems of global computer system of radar complex and existing general avenues applicable to the microprocessor subsystems in digital target return signal processing systems favor using a module structure of target return signal processing systems, the main body of which consists of several identical microprocessor networks. Such microprocessor networks enhance ease of use, reliability, and effectiveness of the digital signal processing system as a whole. However, such microprocessor networks require that the problems of some stages of target return signal processing be parallel. In particular, we have considered such requirement while discussing the noncoherent target return signal preprocessing subsystem. Moreover, there is a need to focus on organizing the control process in such multimicroprocessor network system.

In our case, the control process must be hard; that is, it must be carried out in accordance with a program assigned before and must be subject to the given time sequence. This can be organized by way of instructions to carry out the signal processing and control problems using

5.Module of communication with the user, with interface functions “input–output,” preparation of information for display, and sending information by the communication channel

6.Four central microprocessor networks (three microprocessor networks are working and one microprocessor network is reserve) assigned to solve all problems and tasks of global signal processing and control system, except for the problems and tasks assigned for the coherent target return signal preprocessing subsystem

7.Memory device for cooperative use assigned for the execution of central computer system functions during data processing and control distributed in space and time

8.The structure of the central computer system for global signal processing and control employed by the radar complex gives us an original approximation under solution of the assigned problem. Furthermore, we need to consider all partial signal processing and control algorithms in detail, incorporate these algorithms into the complex signal processing and control algorithm, and design the functional time diagram of the system. This stage of designing must be started after selecting specific types of microprocessor networks and the decision whether it is practicable to continue with a specific process of CRS design and construction

9.7  SUMMARY AND DISCUSSION

The first stage of system design of any radar system is the selection of structure and energy parameters of radar being a constituent of the CRS. The radar antenna type, shape, and width of radar antenna directional diagram, method and period of scanning coverage, transmitter power, duration and scanning signal modulation technique, period of scanning pulsing, resources and methods of protection from active interferences, and other radar parameters must be defined and justified at this stage. At the second stage of CRS design the structure is designed, the parameters of digital signal processing subsystem are justified, and the ways of specific realizations are defined. At the initial stages, the main problems and tasks of digital signal processing and control subsystem should be discussed and the procedures to solve these problems should be defined.

It is worthwhile to employ the rejector filters with the interperiod subtraction of the order ν and the filters of coherent accumulation in the form of FFT processors or filters in series to ensure the required quality of passive interference cancellation and to improve the detection performance of moving targets. Stabilization of the probability of false alarm is also a very important problem. The methods of adaptive threshold control under signal detection are widely used to solve this problem. The implementation of adaptation to the interference and noise power can stabilize the probability of false alarm under detection of target return signals, but, in this case, the average number of false detections is not controlled and can be estimated only during simulation and digital signal processing and control subsystem sample debugging.

Functions such as automatic target lock-in, target trajectory tracking, and target trajectory reset play a vital role and require thorough understanding. A demand to operate in automatic mode under conditions of the high-level interference requires sufficiently effective measures that prevent overloading of the digital signal reprocessing subsystem while processing both the targets that are not captured by the CRS and the false targets. These effective measures are as follows: effective algorithm to detect the target trajectories providing the methods and procedures to decrease the probability of false target track beginning; selection of target pips in target tracking gates taking into consideration the high density of false target pips; filtering the target trajectory parameters providing tracking of both the nonmaneuvering targets and maneuvering targets; implementation of specific algorithms of target classification providing a selection of the most important targets for target tracking; ensuring appropriate speed of operation and memory capacity of central computer system. Under the automatic mode of operation, the most important problem associated with the central microprocessor system is effective control of the CRS as a whole and functional synchronization of operations of all elements. Algorithmic designing and

realization of digital signal processing and control subsystem are other problems to be considered while designing the central computer system.

The principle of division of signal processing procedure into various stages, that is, coherent digital signal preprocessing, noncoherent digital signal preprocessing, and digital signal reprocessing, forms the basis of designing the structure of global digital signal processing and control system of radar complex, which consists of the digital coherent target return signal preprocessing subsystem, digital noncoherent target return signal preprocessing subsystem, digital signal reprocessing subsystem, and digital control subsystem.

The digital coherent signal preprocessing subsystem ensures an interface between the analog receiver linear tract and the central computer system of radar complex. The following important operations are carried out by the digital coherent signal preprocessing subsystem: analog-to-digital conversion; generalized signal processing algorithm of linear-frequency-modulated target return signals; suppression of passive interferences; coherent accumulation of target return signals; and generation of data to solve the problems related to stabilization of the probability of false alarm. The digital coherent signal preprocessing subsystem is realized by individual microprocessor sub-subsystem or distributed set of specific microprocessor subsystems. Choosing the right approach to design and construct the digital coherent signal preprocessing subsystem and justification of structure of the corresponding microprocessor sub-subsystem or set of microprocessor sub-subsystems is the first and foremost requirement of the system design process.

It is worthwhile to employ hardware in the specific digital coherent signal preprocessing subsystem designed based on VLSI microprocessor sub-subsystem to solve the following problems: generalized signal processing algorithm, suppression of passive interferences, computation of target return signal amplitudes, and estimation of interference and noise power. To solve the problems of Doppler filtering, it is worthwhile to implement the FFT processor or filter using effective and simple methods and procedures such as complex multiplication. All elements of the specific digital coherent signal preprocessing subsystem designed based on VLSI microprocessor sub-subsystem must possess high reliability and require low power consumption. High reliability can be achieved by equipment reservation or information redundancy. Low power consumption can be achieved by very careful circuit designing and implementation of VLSI with small power dissipation.

The first element of the global structure of digital coherent target return signal preprocessing subsystem is the ADC of the target return signals at the phase detector output. Next element of the total structure of the digital coherent target return signal preprocessing subsystem is the DGD for linear- frequency-modulated target return signals that can be realized in the time domain employing the nonrecursive filter or in the frequency domain using the FFT processor or filter. To improve the DGD speed of operation, we can use properties of parallelism applied to the matched filtering algorithms. For this reason, to realize the DGD with high speed of operation we can use the parallel mixers based on ROM, parallel adders with simultaneous addition of several numbers, and parallel registers. The nonrecursive smoothing filter with short impulse response is placed after DGD. The main tasks of this filter include the following: first, suppressing the signal side lobes at the DGD output and, second, decreasing the sampling rate to frequency corresponding to requirements of the sampling theorem. A decrease in the sampling rate in m times (m is the integer) is carried out by the element providing a sample of each mth element from sequence of input sampled target return signals {x(kTs)}. The cancellation of correlated interference is realized after the matched filtering. The operations discussed are part of the first stage of the digital coherent signal processing. To ensure the required reliability all hardware elements of the first stage must be doubled. The output signals of the main and reserved hardware set are compared by specific modules. Comparison results are used by both the searching system and the default system.

In accordance with the global structure of digital signal processing and control system used by the radar complex (see Figure 9.1), the noncoherent signal preprocessing subsystem solves the following problems: (a) noncoherent accumulation of signals after the coherent signal processing of each from three 8-pulse bursts by the FFT processor or filter; (b) noncoherent accumulation of interference

and noise power estimations for all Doppler channels, except for the zero Doppler channel, and for all resolution elements by radar range; (c) corrections of the interference and noise power map, forming the adaptive detection thresholds; (d) signal detection to be provided by comparison between the signals and the corresponding thresholds computed for each cell’s “radar range–Doppler frequency”; (e) estimation of the target azimuth by a set of signals exceeding the detection threshold at three neighboring positions of the radar antenna directional diagram by azimuth.

The requirements to speed of operation of the noncoherent target return signal preprocessing microprocessor subsystem are sufficiently high. However, the noncoherent target return signal preprocessing operations can be conducted in parallel using two microprocessor subsystems simultaneously. For example, the first microprocessor subsystem must perform the noncoherent accumulation of target return signals, corrections in the interference and noise power map, and the target azimuth estimation. The second microprocessor subsystem must carry out the noncoherent accumulation of interference and noise power, threshold forming, and signal detection. In this case, the required speed of operation of each microprocessor subsystem is not more than 2 × 103 operations per second.

The main tasks of the digital signal reprocessing subsystem include the following: to realize the target trajectory detection, the target tracking and target trajectory tracking, the filtering of target trajectory parameters, and other digital signal processing algorithms accomplished during the target processing stages, and to provide precise information to the user. The analysis performed thus shows that the digital signal reprocessing problems do not require the high computational resources in comparison with the previous stages of target return signal processing. This fact allows us to assign for the digital signal reprocessing microprocessor subsystem the problems of control over all elements and parameters of the CRS and the current hardware and computational process control problems. Taking into consideration that the control optimization problems are not solved in dynamic mode in the automatic “radar complex–global digital signal processing complex” system and the control system is constructed as the system with a fixed, predetermined sequence of control commands.

Functional requirements, cost, reliability, conveniences in fault lookup, maintainability are the important factors that are taken into consideration in the course of designing the global digital signal processing structure of the CRS. The functional requirements to individual elements of this structure discussed and considered previously are evidences of differences in the density of information flow processed by the central computer system of radar complex. The digital coherent target return preprocessing subsystem working in real time has the greatest service load. For this reason, and given the technological breakthroughs in the signal detection and signal processing theory and computer applications, there is a need to design and construct a specific nonprogrammable microprocessor subsystem for the digital coherent target return preprocessing subsystem working in real time, which consists of the specific adders, mixers, convolution networks, memory devices based on VLSI and charge-injection devices. Without any doubts, we can state that the possibility of designing and constructing such specific microprocessor subsystems is the foundation stone for developing processes that solve the problems encountered in automatic digital target return signal processing in the functioning of the CRS under real-time conditions.

REFERENCES

1.Moon, T.K. and W.C. Stirling. 2000. Mathematical Methods and Algorithms for Signal Processing. Upper Saddle River, NJ: Prentice Hall, Inc.

2.Billingsley, L.B. 2002. Low-Angle Radar Land Clutter—Measurements and Empirical Models. Norwich, NY: William Andrew Publishing, Inc.

3.Richards, M.A. 2005. Fundamentals of Radar Signal Processing. New York: McGraw Hill, Inc.

4.Levy, B.C. 2008. Principles of Signal Detection and Parameter Estimation. New York: Springer Science + Business Media, LLC.

FIGURE 10.1  Global digital signal processing system structure.

of the gated area of radar coverage. The target return signals received by gates after an analog-to-digital converter (ADC) come in at the input of MTI selected by the dispatch device and are processed by MTI. Initial values of target trajectory parameters determined by the digital signal reprocessing microprocessor network are used by MTI at the first stage of accurate definition of the target trajectory parameters. Furthermore, the extrapolated coordinates of gate centers and dimensions are computed and are sent to the device of physical gating by corresponding MTI networks. Under unspecified reset action of target trajectory tracked by MTI, the target relockin is carried out using the global digital signal processing system rough channel. The considered structure of the global digital signal processing system possesses a high reliability and requires moderate designing charges and operating costs.

10.1.2  Structure and Operation of Nontracking MTI

Let us consider the nontracking MTI system. The nontracking MTI is the microprocessor network for digital signal processing. The signals come in at the nontracking MTI input from the radar coverage zone limited by the physical gate. The nontracking MTI structure is shown in Figure 10.2, which shows that the nontracking MTI possesses the same functions as those under the target tracking. The essential difference is matching the signal preprocessing operations with a selection of target pips in the target tracking gate. In doing so, owing to limiting gate dimensions it is possible to realize the signal quantization and signal processing algorithms. As to the target trajectory parameter smoothing operations, the nontracking MTI ensures the maneuvering of target tracking.

Consider in detail the signal preprocessing and selection in the target tracking gate algorithm. The problems of target detection, definition of target position, and selection of target return signals within the limits of gate are reduced to checking several hypotheses. Moreover, a signal absence in the gate is considered as the hypothesis 0, and the alternative hypotheses are the hypotheses about the signal presence in a single (or several) gate cell. We consider the gate cell as the gate volume (or square) element limited by sampling intervals on the radar range, azimuth, and tilt angle coordinates. An optimal procedure under processing the observation results with the purpose of checking the statistical hypotheses is a generation of the likelihood ratio and its comparison with the threshold that is selected from acceptable losses attributed to correct or incorrect decisions. Furthermore, we consider the signal processing algorithm of binary signals in two-dimensional