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in at the input of another microprocessor; that is, the microprocessors process information sequentially or in conveyer style. The conveyer style of digital signal processing is based on partition of the digital signal processing algorithm on a set of steps and matching in time these steps when the digital signal processing algorithm is accomplished. Advantages with the implementation of the backbone multimicroprocessor subsystems compared to the matrix homogeneous multimicroprocessor ones are the moderate requirements with respect to inner coupling and simplicity with which the backbone multimicroprocessor subsystem’s computational power can be increased. Disadvantages are removed by organizing a priority exchange of information between the system cells.

Two types of the backbone multimicroprocessor subsystems are widely used for digital signal processing in real time: the first type, a one-dimensional inner long-distance channel operating in the time-sharing mode, and the second type, a multidimensional inner long-distance channel coupled with two-input RAM. In the backbone multimicroprocessor subsystem of the first kind all RAM and ROM, CMP, and SMP are combined by the same channel. There is a block to control the channel. This block is used in the case of conflict situations when several microprocessors address RAM simultaneously and for controlling data upload and extraction using the channel units to exchange the data. Operation of a single backbone multimicroprocessor subsystem is carried out in the following way. Each microprocessor submits, as needed, an application to the channel to address to RAM or ROM. If the channel is free then the microprocessor can access RAM or ROM immediately. Otherwise, the microprocessor is in the idle mode. The microprocessor can access RAM or ROM when the previous queries from other microprocessors are ended and there are no further high-priority queries from microprocessors. Consequently, there are high requirements to the information channel with respect to the data channel throughput. Determination of the required throughput is carried out for each specific case using methods of the queuing theory. Finally note that the said structure of the backbone multimicroprocessor subsystem has limited speed of operation defined by the data channel throughput and, in addition, with the data channel failure, the backbone multimicroprocessor subsystem stops any operation. A great advantage of the backbone multimicroprocessor subsystem is its simplicity. In the backbone multimicroprocessor subsystem with the multidimensional inner long-distance channel, all microprocessors operate using independent asynchronous mode and all conflict situations are practically excluded. This system has very high reliability and allows us to increase the performance without any limitations. Disadvantage of the backbone multimicroprocessor subsystem with the multidimensional inner long-distance channel is the high complexity caused by the use of multiinput RAM and ROM. While designing the multimicroprocessor subsystem, the main problem is to provide the required performance by selecting the number of microprocessors to be included in the structure of this subsystem. With an increase in the number of microprocessors in the multimicroprocessor subsystem structure, a portion of overhead caused by a waiting time while microprocessor addresses RAM or ROM, simultaneously addressing common tables and operational systems, and the timetables caused by operation of the supervisory routing increase too.

The microcomputer constructed based on a microprocessor possesses high reliability and flexible universality; however, speed of operation is low. In this case, the required performance for CRS digital signal processing can be realized by organization of multiple microcomputer systems using several microprocessors. Such computer systems are called the microprocessor systems. In any microprocessor subsystem there must be an organized network providing communication between the microprocessor subsystem elements for data exchange between microcomputers. Configuration and the degree of complexity of such communications depend on the CRS digital signal processing algorithms, the distribution of operations between the microcomputers, and the acceptable number of RAM used by one microcomputer.

The QS interacts with sources of requests for queuing. In the discussed case, the targets and other interferences being in the radar coverage are considered as the sources of queuing requests. These sources interact with the QS by a request sensor—the CRS plays this role. Radar system transforms the queuing request into signals that are subjected to process. Time sequence

of these signals, which is ordered during radar sensing and scanning of the controlled space, forms an input request flux for the QS. The incoming flux request service is organized by the QS. The QS can be considered as both the device carrying out a direct request service and the device assigned to store a request queue meant for service. The QS is characterized by the following: (a) the number of devices (cells) assigned to store a request queue of the incoming signal flux (the IBA memory size); (b) the number of devices (channels) K that can serve the requests simultaneously; (c) the number of devices (cells) to accumulate and store the results of digital signal processing (the IBA memory size). The request queue is stored by IBA of microprocessor subsystem. The waiting time and the number of queued requests (the request queue length) are the random variables depending on statistical parameters of the incoming signal flux and service rate. Because the IBA size (memory capacity) is limited, the request queue length and, consequently, the waiting time of request queue are limited too. This QS is called the QS with the limited queue (the limited waiting time). Thus, the digital signal processing subsystem can be considered as the subsystem belonging to the class of QSs with limited queue.

The process of selecting a new request from a set of requests waiting queuing involves the following. After digital signal processing of immediate request, the supervisory program investigates sequentially queuing and selects for service the request possessing the greatest priority. After initiation of the corresponding routine, it is realized by the microprocessor. The queued request leaves the system, and a control is transferred to the supervisory routine again. If there are no further requests, then the supervisory routine switches on the microprocessor in the idle mode. At each instant, the microprocessor can run a single program only. For this reason, the considered QS is called a single-channel or a single-microprocessor QS.

As a rule, we need to exercise strong limitations with respect to the waiting time for request queuing of individual signal fluxes that require assigning them by absolute priorities, for example, the requests to process the target return signals. Other requests have excess waiting time and may be assigned by relative priorities. Several requests can be served by the simple queuing procedure. Thus, we see that we need to apply mixed regulations for request queuing, investigation of which is carried out for each specific case by simulation procedures.

The required effective speed down boundary definition of the third type of control singlemicroprocessor subsystem operation can be considered as the initial stage of designing the microprocessor subsystem for CRS digital signal processing. The next stage involves choosing the optimal request queuing regulation. At the system design stage, we will not have sufficient information to choose the specific request queuing regulation, but we should take into consideration the following circumstances: (a) the request queuing regulation based on request queuing in turn to come in at the control single-microprocessor subsystem possesses the best performance among all the nonpriority request queuing regulations; in particular, in this case, the variance of the request queuing waiting time is minimum compared to other nonpriority request queuing regulations; (b) introduction of the priority request queuing regulation allows us to decrease essentially the request queuing waiting time for the most important requests of signal flux owing to increased delay during the queuing of signal minor fluxes; (c) in general, introduction of the priority request queuing regulations provides an equivalent performance of the control single-microprocessor subsystem compared to the request queuing one in turn. Consequently, the aforementioned values of the required minimum speed of control singlemicroprocessor subsystem operation provides a possibility to choose the priority request queuing regulation without any additional increase in the effective speed of operation. The minimum value of the effective speed of operation ensures the boundary values of the request queuing waiting time of the earlier-considered types of the request queuing regulations for the control single-microprocessor subsystem and related to a queue length that can be defined for

the kth signal flux as lk = λktwait k. Queue existence and its store are related to definite losses. To decrease these losses, the effective speed of control single-microprocessor subsystem opera-

tion must be greater than minimal one. However, in this case, the loading factor U decreases

and, correspondingly, the idle time factor Q = 1 − U increases, which is not good from the point of view of hardware costs.

Requirements for RAM size and structure are defined based on the end use of the system, character and digital signal processing algorithms, and analysis of input and output signal fluxes. As a first approximation, the total RAM size (memory capacity) is defined from the formulas QΣ =

Qroutine + Qdigit, where Qroutine is the RAM cell array assigned to store the routines of digital signal processing algorithms, control routine of computational process and operation of whole system,

interruption routines, and routines controlling calculations; Qdigit is the RAM cell array assigned

to store a numerical information. In turn, Qdigit can be presented in the following form: Qdigit = Qin + Qworking + Qout, where Qin is the RAM cell array assigned to receive external information; Qworking is the RAM cell array participating at the calculation process; Qout is the RAM cell array assigned

to store the results of digital signal processing. In many cases, the relative independence of routine information on numerical one leads us to expediently use individual permanent memory or ROM to store the routine information. ROM uses only a reading mode. Implementation of ROM gives us a great advantage because information stored by ROM is not lost even if the power is off. In addition, ROM possesses high reliability. As for ROM size (capacity), at the initial stage of designing the digital signal processing subsystem it is possible to estimate this parameter approximately. The exact estimation is possible only after program debugging.

The problem with choosing the special-purpose microprocessors is solved based on requirements for making demands to the designed microprocessor subsystem on speed of operation, RAM and ROM sizes, and technical characteristics, reliability, overall dimensions, use, cost, and other requirements. Selection of the appropriate microprocessor depends on the degree of correspondence between a set (vector) of QoS of the selected microprocessor and a set (vector) of requirements to these quality indices. A numerical measure or criterion of effectiveness must be established to compare the selected microprocessors. However, at the initial stages of designing it is very difficult, as a rule, to establish a function between the parameters of microprocessor and generalized criterion of effectiveness as a whole. Moreover, selection of the generalized criterion, demonstrable and convenient in computational sense, is not easy. We can obtain the following results of comparison between the microprocessor parameters: (a) only one type of microprocessors from existing nomenclature satisfies all requirements; (b) none of the microprocessors from existing nomenclature satisfies all requirements; and (c) there are several types of microprocessors from existing nomenclature satisfying all requirements. In the first case, only the microprocessor that satisfies all requirements is selected to design the microprocessor subsystem. In the second case, we need either to correct the requirements based on simplification of digital signal processing algorithms for solved problems and change an environment or to make a decision to construct a multimicroprocessor subsystem based on implementation of microprocessor of the same or different types produced by industry. In the third case, the problem with selecting the best microprocessor satisfying all requirements is solved. In this case, there are several ways to make this choice. We consider the simplest way—the ranking way.

While designing the structure of microprocessor subsystem for CRS digital signal processing of target return signals we need to consider a sequence of digital signal processing step realization and the difference in the scale of real time for each step involved in digital signal processing. An important initial condition for the synthesis of microprocessor subsystems is the selection of appropriate hardware and software that as a unit helps to solve the problems associated with CRSs. A total set of the microprocessor subsystem hardware can be divided into the following groups: (a) the microprocessor subsystem facilities providing a realization of CRS digital signal processing algorithms;

(b) the communication facilities providing transmission of information from sources to users; (c) the facilities of transmission of information; and (d) the interface and commutation facilities assigned to unify the microprocessor subsystem facilities into the multimicroprocessor subsystems for the purpose of increasing the speed of operation and reliability of computations and numerical calculations. Naturally, the main microprocessor subsystem element defining its structure is a system of

computing facilities. Two types of computing facilities are employed by the digital signal processing subsystems, namely, the control microprocessor subsystem and the multimicroprocessor subsystems for specific applications providing a realization of the main digital signal processing and control algorithms, and the special-purpose high-performance microprocessors assigned mainly for target return signal filtering at the stages of the intraand inter-period digital signal processing. The other aforementioned hardware facilities are special purpose and are assigned for SMP subsystems implemented in CRSs of special-purpose application. Questions of rational selection of hardware facilities for designing the microprocessor subsystem are essential because, in the case of specialpurpose applications, dimensions and cost of such SMP subsystems outweigh the corresponding characteristics and performance of usual microprocessor systems.

Software is the programmable facility system assigned to increase the effectiveness of employing a microprocessor subsystem and decrease the work content of preliminary operation for the solution of problems by microprocessor subsystem. Software can be divided as internal and external software. In the control microprocessor, the internal software consists of the automized programming routine, operating system routine, that is, computational process control routine, and functioning control routine. The external software consists mainly of the application program library and the specific programs of CRS digital signal processing. Because the cost of designing software exceeds the cost of designing hardware, one of the main avenues of the microprocessor subsystem development is the realization of some typical software functions by hardware.

The main problems with improving the structure and elements of the considered microprocessor subsystems are the following: (a) to design the high-performance signal microprocessors for digital signal processing of target return signals, taking into consideration solutions for both considered and discussed problems and new problems (obviously, one way to solve this problem is to further specialize the special-purpose microprocessors and to introduce parallel algorithms for solving the digital signal processing of target return signal problems); (b) to design and construct high-performance parallel (matrix, conveyer, and other types) microprocessors based on modern and perspective element base providing the required performance during the automation of all main problems of CRS digital signal processing of target return signal and control process; and (c) to design and construct the microprocessor subsystems with uniformly and nonuniformly distributed structure satisfying requirements of unification of digital signal processing hardware oriented to the special-purpose applications.

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While designing a specific digital signal processing and control system, theoretical and technical investigations on signal processing methods and algorithms, the technical team, including engineers and subject experts, communications skills, and so on play a very important role.

9.2  DESIGN OF DIGITAL SIGNAL PROCESSING AND CONTROL SUBSYSTEM STRUCTURE

9.2.1  Initial Statements

In accordance with the basic idea, let the designed CRS be assigned for air target detection and tracking with a highly effective reflective surface Stg ≥ 1 m2. Scanning area is omnidirectional. The maximum radar range is Rmax ≤ 150 km (T = 1 ms). Information is presented to users via the smoothed polar coordinates ρˆ tg and βˆ tg, the target course Qˆ tg, and the velocity scalar of vector Vtg. The accuracy of smoothed coordinates and parameters are σρ = 500 m, σβ = 0.5°, σQ = 2°, and σV = 50 m/s.

The CRS must distinguish the targets from the background of passive interferences with the coefficient of distinguishability that is sufficient for target detection and target tracking while the target and passive interference are resolved. Moreover, the system must be able to detect a stationary target, or a moving target with the so-called blind velocities, for which fD = kT−1 (k = 1, 2, …). The problem with detecting the target at the border of scanning range with the probability of detection PD = 0.95 is set within the time limits of 15 s. The probability of target-tracking failure within the

limits of scanning range is Pfailure ≤ 0.05. The maximum number of targets tracking simultaneously is Ntg = 20. All CRS operations, namely the target detection, the lock-in for target tracking, and the

target tracking by trajectory, must be automated completely. The reliability control measures allowing the CRS to operate without a regular labor force must be provided.

The first stage of any radar system design involves the selection of radar structure and energy parameters constituent of a CRS. The radar antenna type, shape and width of radar antenna directional diagram, method and period of scanning coverage, transmitter power, duration and scanning signal modulation technique, period of scanning pulsing, resources and methods needed for protection of the system from active interferences, and other radar parameters must be defined and justified at this stage. Thus, as a result of the first-stage activities, we have the following:

•The cylindrical antenna is selected as the transmit–receive antenna, which makes discrete scanning possible as facilitated by the radar antenna’s directional diagram beam in omnidirectional scanning mode. The radar antenna directional diagram beam is

fan-shaped in the vertical plane and covers all scanning range by tilt angle. The radar

antenna directional diagram beam width in the horizontal plane is θβ = 3°. Scanning resolution is equal to 2.5°. The number of fixed positions of the radar antenna directional diagram under the omnidirectional scanning is equal to 144. The omnidirectional scanning period is Tscan = 4.5 s.

•The linear-frequency-modulated pulse with duration τscan = 64 μs and spectrum bandwidth fscan = 0.5 MHz is considered as the scanning signal. The scanning signal base is τscan fscan = 32. Duration of the compressed signal at the GD output is τscancomp = 2 µs.

•The power of scanning signal is selected in such a way that each direction is scanned by the pulse bursts consisting of 30 pulses divided on groups, each of 10 pulses at three con-

vertible in series frequencies f01 , f02 , f03 diverging on the constant interval f0 to satisfy the required signal-to-noise ratio (SNR). The coherent accumulation of reflected signals for each group of 10 pulses and the noncoherent accumulation of corresponding total signals in each resolution element by radar range, azimuth, and Doppler frequency between groups must be provided.

Note that specific magnitudes of some radar parameters are presented here only because they are directly used in the designing and construction of a CRS digital signal processing and control subsystem.

At the second stage, the design process involves the following key steps: specifics related to the CRS structure are firmed up, the parameters of digital signal processing subsystem are justified, and the ways of specific realizations are defined. Foremost, the main problems and tasks of digital signal processing and control subsystem should be discussed and the procedures to solve these problems should be defined.

9.2.2  Main Problems of Digital Signal Processing and Control Subsystem

The task of running a CRS operation in automatic mode is carried out based on the data gathered at the initial stage of designing. Successful running of this operation is foremost achieved by high-quality cancellation of the passive interference formed due to reflections from the underlying surface, local objects, and hydrometeors. It is universally accepted that in the automatic mode the coefficient of cancellation ηcan of the passive interference caused by reflections from the underlying surface and local object should not be less than 50 dB and, by reflections from the hydrometeors, it should be approximately 30 dB.

To cancel the passive interference, the moving target indicator systems based on the rejector filters with interperiod subtraction of the order ν are widely used. However, in the case of high-density nonstationary passive interferences, the moving target indicator systems based on the rejector filters with the interperiod subtraction of the low order, ν = 2/3, cannot ensure the required SNR at the output. Using the moving target indicator systems based on the rejector filters with the interperiod subtraction of the high order ν increases blind velocity zone that adversely affects the detection performance, especially for targets moving in directions tangential to the radar antenna directional diagram main lobe. The coherent signal processing technique of target return pulse bursts is effective for improving the detection performance of moving targets and decreasing the rate of stimulation of blind velocities. This signal processing method can be carried out using the fast Fourier transform (FFT) processors or filters. Thus, it is worthwhile to use the rejector filters with the interperiod subtraction of the order ν and the filters of coherent accumulation in the form of FFT processors or filters in series to ensure the required quality of passive interference cancellation and, thus, better performance in detecting moving targets.

The number of pulses in the scanning pulse burst at each of the three carrier frequencies f01 , f02 , f03 is defined based on the condition to use the rejector filters with the interperiod subtraction of the order ν = 2 and 8-point FFT for coherent accumulation of target return signals within the limits of the pulse burst in the digital signal processing subsystem. In this case, the noncoherent accumulation of target return signals of three pulse bursts for each resolution element by radar range and for each Doppler channel must be provided. Variations in the carrier frequency of scanning pulses from burst to burst lead to a corresponding shift in the Doppler frequency of moving target return signals. The main effect of this shift is that the task of identifying the return signals from the same target becomes difficult, particularly because these return signals can appear in different Doppler channels. Thus, to eliminate this shift in the Doppler frequency of return signals from the same target at different channels of frequency, we need to select the period of scanning signals at each pulse burst in such a way that the following condition

could be satisfied. Actually, at Vtg = const for each frequency f0i, the Doppler frequency is defined as

On the other hand, the maxima position of the impulse response from the N-channel FFT processor or filter depends on the scanning pulse frequency

To ensure the coincidence of the Doppler frequency with the tuning frequency of the lth channel, the following inequality needs to be satisfied:

At l = constant, the first part in (9.4) is the constant value and the condition f0iT = const follows. As noted in Chapter 3, to decrease the side-lobe level of amplitude–frequency characteristic of the

Doppler channels, the signal weighting at the output of the FFT processor or filter is applied using the windows with the symmetric negative-going to end characteristics. In practice, the Hemming window is often used for signal weighting [1], wherein the computation of weighted signal readings at the in-phase and quadrature channels at the FFT processor or filter output is carried out as shown in the following algorithm:

where

fl weight is the weighted signal at the output of lth Doppler channel

fl−1, fl, fl+1 are the nonweighted signals at the outputs of l − 1th, lth, and l + 1th Doppler channels, respectively

In this case, the signal weighting based on the algorithm given by (9.5) is carried out at the Doppler channels with l = 2–6. Further, there is a need to note that the FFT processor or filter accomplishes the coherent accumulation of target return signals if the targets move with zero radial velocity, which makes the target detection an easy task.

Maintaining stability of the probability of false alarm is also an important task. The use of adaptive threshold control under signal detection is a practice commonly followed in solving this problem. The functioning principle of adaptive detector at the FFT processor or filter Doppler channel output is as follows. Estimation of the interference and noise variance inside the moving window of the width −0.5 to 0.5 m is defined at the outputs of all Doppler channels, excluding the zero Doppler channel, by the following formula:

where i is the number of radar range resolution element with respect to signal element, for which the average power level of interference and noise is estimated (the signal element is the central one);

0, i = j − 1, j, j + 1;