Diss / 10

8.3  REQUIREMENTS FOR RAM SIZE AND STRUCTURE

Requirements for RAM size and structure are defined based on the end use of system, character and digital signal processing algorithms, and an analysis of input and output signal fluxes. As a first approximation, the total RAM size (memory capacity) is defined from the formula

where

Qroutine is the RAM cell array assigned to store the routines of digital signal processing algorithms, control routine of computational process and operation of whole system, interruption

routines, and routines controlling calculations

Qdigit is the RAM cell array assigned to store a numerical information

In turn, Qdigit can be presented in the following form:

where

Qin is the RAM cell array assigned to receive external information

Qworking is the RAM cell array participating at the calculation process

Qout is the RAM cell array assigned to store the digital signal processing results

In many cases, the relative independence of routine information on numerical one leads us to expediently use individual permanent memory or ROM to store the routine information. ROM uses only a reading mode. Implementation of ROM gives us a great advantage because information stored by ROM is not lost even if the power is off. In addition, ROM possesses high reliability. As for ROM size (capacity), at the initial stage of designing the digital signal processing subsystem it is possible to estimate this parameter approximately. The exact estimation is possible only after program debugging.

Now consider some ways of choosing the size (capacity) of memory to be assigned to store the numerical information. The cell array Qout forms a buffer memory. The buffer memory size depends on the number of external objects, information content incoming from each object within the limits of digital signal processing cycle, microprocessor operation speed, request queuing regulation, and so on. Consider the example of the control single-microprocessor subsystem receiving information from a 3D CRS with the space periodical scanning. Assume that the number of scanned targets is Nscantg . Information about each target at the control single-microprocessor subsystem input (the target pip) includes the spherical coordinates of the current target position and the variance of error for the measurement of these coordinates. We assume that the coordinate code width and coordinate measurement errors are established at the previous stages of digital signal processing and is characterized by the number of binary digits np for each target pip. Digital signal processing procedure must be organized in such a way that information obtained during the previous cycle would be completely processed during the next cycle. Thus, during the cycle equal to the

scanning period, Nscantg of np-digit words will be recorded in the buffer memory. If we assume that a target distribution in the radar coverage is uniform, the target pip flux at the buffer memory input

conforms to Poisson law, and there is the nonpriority request queuing regulation at the control single-microprocessor subsystem, then the queue length of request queuing can be determined in the following form:

specific procedures to form arrays. In addition to the required number of RAM cells determined by (8.46), an array of working cells to store the intermediate results of computations needs to be envisaged. In the case of the considered example, during the sequential realization of the linear filtering algorithm in accordance with the graph depicted in Figure 7.13, the number of cells in this array is not more than s2. RAM is the main memory of any microprocessor subsystem and is constructed in the module form.

The cell array Qout serves to store the numerical information assigned to transfer results of the digital signal processing of the target return signals to external objects. This cell array, as well as the cell array Qin, is the BA to communicate with users. For this reason, a determination of the number of array cells, that is, the size (capacity) of the array Qout, as well as the number of array cells of the array Qin is carried out analogously. Finally, note that the specification of requirements to the RAM size is carried out simultaneously (in parallel) with the specification of requirements to the microprocessor subsystem operation speed.

8.4  SELECTION OF MICROPROCESSOR FOR DESIGNING THE MICROPROCESSOR SUBSYSTEMS

The task of choosing the special-purpose microprocessors is accomplished based on the requirements for making demands to the designed microprocessor subsystem in terms of speed of operation, RAM and ROM sizes, technical characteristics, reliability, overall dimensions, use, cost, and other requirements. Choosing the appropriate microprocessor depends on the degree of correspondence between a set (vector) of quality of service (QoS) of the selected microprocessor and a set (vector) of requirements to these quality indices. A numerical measure or criterion of effectiveness must be established to compare the selected microprocessors. However, at the initial stages of designing it is very difficult, as a rule, to establish a function between the parameters of microprocessor and generalized criterion of effectiveness as a whole. Moreover, selection of the generalized criterion, demonstrable and convenient in computational sense, is not easy. In what follows, we consider a simple procedure for selecting the appropriate microprocessor.

Let a nomenclature of microprocessors produced by industry form a set

where m is the number of microprocessor. Each element of the set (8.47) is defined by the totality

where n is the number of parameters taken into consideration. Let

be the set of requirements to the microprocessor subsystem.

Selection of serviceable microprocessors is to find in the set M = {Mi}1m one or several microprocessors satisfying the given specifications and requirements {K j}1m. At the same time, the following results of comparison between the microprocessor parameters and set of requirements K are possible:

•The only type of microprocessors from existing nomenclature satisfies all requirements.

•None of the microprocessors from the existing nomenclature satisfies all requirements.

•There are several types of microprocessors from existing nomenclature satisfying all requirements.

In the first case, the only microprocessor satisfying all requirements is selected to design the microprocessor subsystem. In the second case, we need either to correct the requirements based on simplification of digital signal processing algorithms for solved problems and change an environment or to make a decision to construct the multimicroprocessor subsystem based on the implementation of microprocessor of the same or different types produced by industry. In the third case, the problem of selecting the best microprocessor satisfying all requirements is solved. In this case, there are several ways by which one can make this choice. We consider the simplest way—the ranking way that is described as follows.

Let the microprocessor requirements be ranked in decreasing order of their importance, for example, in the following sequence: K1 is the reliability, K2 is the weight, K3 is the power, and so on. The parameters of compared microprocessors are ranked in the corresponding order. Then if the first by rank (importance) parameter of some microprocessor is essentially better than others, then independent of the remaining parameters this microprocessor is considered the best. If several microprocessors have the same first parameter, then the second parameter is analyzed and the microprocessor with the highest second-rank parameter is considered as the best microprocessor and so on. This selection is continued until there is only one microprocessor left to be selected. Optimization procedure is multistage and involves sequential reduction of the number of considered microprocessors. In the theory of optimal system designing, this method is called the sequential increasing of resolution level of the applied criterion of effectiveness.

8.5  STRUCTURE AND ELEMENTS OF DIGITAL SIGNAL PROCESSING AND COMPLEX RADAR SYSTEM CONTROL MICROPROCESSOR SUBSYSTEMS

For designing the microprocessor subsystem structure, first of all, we should take into consideration the content and characteristics of problems that must be solved. Recall that the digital signal processing subsystem in an automated CRS must carry out the following problems:

•Intraperiod digital signal processing of the target return signals with the speed defined by the period of discretization td

•Interperiod digital signal processing of the target return signals with the speed defined by the period T of scanning the signals pulsing

•Intersurveillance digital signal processing of the target return signals with the speed

defined by the period Tsc of scanning the radar coverage during target detection or the period of refreshment Tnew during target tracking

Thus, for designing the microprocessor subsystem structure for CRS digital signal processing of target return signals we need to consider a sequence of digital signal processing step realization and difference in the scale of real time for each step in digital signal processing. An important initial condition for the synthesis of microprocessor subsystems is the selection of hardware and software that as a unit helps to solve the problems assigned for CRSs. A total set of microprocessor subsystem hardware can be divided on the following groups:

•Microprocessor subsystem facilities providing a realization of digital signal processing algorithms

•Communication facilities providing transmission of information from sources to users

•Facilities of transmission of information

•Interface and commutation facilities assigned to unify microprocessor subsystem facilities into multimicroprocessor subsystems for the purpose of increasing speed of operation and reliability of computations and numerical calculations

Naturally, the main microprocessor subsystem element defining its structure is a system of computing facilities. Two types of computing facilities are employed by digital signal processing subsystems, namely,

•The control microprocessor subsystem and multimicroprocessor subsystems for specific applications providing a realization of the main digital signal processing and control algorithms

•The special-purpose high-performance microprocessors assigned mainly for target return signal filtering at the intraand inter-period digital signal processing stages [20–22]

Other foregoing hardware facilities are special purpose and assigned for SMP subsystems implemented in special-purpose CRSs. Questions of rational selection of hardware facilities for designing the microprocessor subsystem are essential because, in the case of special-purpose applications, dimensions and cost of such SMP subsystems outweigh the corresponding characteristics and performance of usual microprocessor systems.

Software is the programmable facility system assigned to increase the effectiveness with which the microprocessor subsystem is used and decrease the work content of preliminary operation for the solution of problems by the microprocessor subsystem. Software can be divided into internal and external software. In the control microprocessor, the internal software consists of the automized programming routine, operating system routine, that is, computational process control routine, and functioning control routine. The external software consists mainly of application program library and specific programs of CRS digital signal processing. Since the cost of designing software exceeds the cost of designing hardware, one of the main areas in microprocessor subsystem development is the realization of some typical software functions by hardware.

In general, the microprocessor subsystem structure is defined by the hardware facilities, for example, microprocessors, controllers, interface, and so on, and ways to combine the hardware in a system, to organize a computational process, to exchange information between some elements of the microprocessor subsystem, to expand the microprocessor subsystem for obtaining high performance, to organize logically combined operation of various elements of the microprocessor subsystem. On the basis of these general thoughts and taking into consideration the specific character of the solved problems, we can classify the microprocessor subsystems of CRS digital signal processing in the following form:

1.The microprocessor subsystems with complete host subsystem structure, for which there are the CMPs controlling digital signal processing and a set of interface processing modules (the microprocessors, the memories, etc.) operating under control of the CMP. In this case, the CMP must possess an extremely effective speed of operation (we consider an example of such microprocessor subsystem in the next section).

2.The microprocessor subsystems with the so-called federal structure, for which some special-purpose microprocessors assigned for digital signal processing operate in the free-running mode and can be considered as maintainable CRS equipment. Combination of information with the outputs of-line microprocessors and digital ­signal processing ending taking into consideration all interests of users are carried out by the CMP. Federated control of the microprocessor subsystems is carried out by the CMP.

As an example, a microprocessor subsystem version with the federal structure for digital signal processing and control in CRSs for detection and target tracking is depicted in Figure 8.11. Independent devices of the microprocessor subsystem are the signal microprocessors carrying out a digital signal processing of target return signals received using an interface device. There are several such microprocessors and each of them operates in its own timescale

FIGURE 8.11  Microprocessor subsystem with federal structure.

in accordance with the realized step of digital signal processing. The processed information, that is, target pips, comes in at the input of central block over the buffer accumulator (BA1), in our case, the microprocessor special-purpose subsystem. The CMP solves a digital signal reprocessing and other problems interested for users are solved. The processed information comes over the BA2 and data bus at the inputs of the control and display subsystems, documenting and transferring data subsystems (DTDS). Additional digital signal processing is also realized by these subsystems using the off-line units. Control process in the considered microprocessor subsystem is carried out only for the purpose of operation plans and adaptation to the changing environment and character of solved problems. Control operation can be carried out by the individual control processors and synchronization of CRS hardware.

3.The microprocessor subsystems with a completely decentralized structure, both in space and functionality, in which the local digital signal processing blocks solve the problems in the off-line mode or under the control of one block. This microprocessor subsystem allows us to increase principally the digital signal processing performance owing to the specialization of blocks carrying out the numerical calculation and best matching their structure with specific character of the realized digital signal processing algorithms. An obvious disadvantage of this microprocessor subsystem is a complexity involved in controlling this subsystem, but there are no doubts that this disadvantage can be overcome and the distributed microprocessor subsystem of digital signal processing of target return signal would be widely used in practice.

The main problems with improving the structure and elements of the considered microprocessor subsystems are as follows:

•To design high-performance signal microprocessors for digital signal processing of target return signals taking into consideration solutions for both the considered and discussed problems and new problems. Obviously, one way to solve this problem is further specialization of the special-purpose microprocessors and introduction of parallel algorithms to solve the digital signal processing of target return signal problems.

and so on. The speed of operation of the microprocessor subsystem allows us to solve the problems of Doppler filtering. For this purpose, the FFT microprocessor is used.

3.The RAM as a set of RAM modules. These RAM modules can be coupled with other microprocessor subsystem elements using CB.

4.The interface with external objects includes 8 bidirectional I/O channels ensuring transmission of 32 digits per word. In addition, there is a wideband channel of direct memory access.

5.The control microprocessor assigned to solve the control problems of the microprocessor subsystem is realized as the 32-digits-per-word programmable microprocessor including RAM of larger size (capacity) and microinstruction memory.

Thus, the considered programmable microprocessor subsystem provides for the individual realization of digital signal processing using two real timescales: the intraperiod digital signal processing using the input programmable microprocessor of real time and the interperiod digital signal processing using the arithmetical microprocessor. The programmable microprocessor subsystem can be implemented in combination with a wide range of CRSs for target detection and tracking with mechanically rotating antenna. If requirements for speed of operation and memory size (capacity) cannot be satisfied by using a single-programmable-microprocessor subsystem, we can apply the programmable multimicroprocessor subsystem with controller.

8.8  SUMMARY AND DISCUSSION

To compare the microprocessor systems between each other we can consider the following engineering data: addressness—the number of address codes used by the instruction code; number representation capacity—the control microprocessor systems are characterized by 16, 24, 32, and 64 digits per word; number representation form—there are two number representation forms: the fixed and the floating point; microprocessor speed of operation—to characterize the speed of operation of the microprocessor subsystem the statement of “rated speed” is introduced independent of the solved problem class; effective speed of operation—the average number of operations per second for the realization of the specific digital signal processing algorithm.

One of the possible ways to increase the microprocessor subsystem performance and reliability for digital signal processing in real time is to design and construct the CRS multicomputer subsystems for effectively using the digital signal processing algorithms. Computational process in the multicomputer subsystems is organized using new principles, namely, a parallel digital signal processing by several microprocessor subsystems. The main factors defining such a multicomputer subsystem structure include the end use, required performance, and memory size for the solution of given problem in totality and functional reliability taking into consideration external environment and economical factors—admissible cost and admissible energy consumption.

The homogeneous multicomputer subsystem constructed based on the principles of adjustment operation, operation of information exchange, operation of generalized conditional jump, and operation of generalized unconditional jump allows us to realize any digital signal processing algorithms. In other words, this is universal subsystem in algorithmic sense. These homogeneous multicomputer subsystems do not have any limitations in performance for the computation of complex digital signal processing algorithms and allow us to ensure the required reliability and subsystem survival under the assumption of unlimited number of elementary cells (microprocessors). The designing problem for the homogeneous multicomputer subsystems is to define the number of elementary cells ensuring the realization of the complex digital signal processing algorithms in real time and required operational reliability taking into consideration the multicomputer subsystem losses in the effective speed of operations.

The backbone multimicroprocessor subsystem combines several independent microprocessors coupled with each other in such a way that information at the output of one microprocessor comes