8 Design Principles of Digital Signal Processing Subsystems Employed by a Complex Radar System
8.1 STRUCTURE AND MAIN ENGINEERING DATA OF DIGITAL SIGNAL PROCESSING SUBSYSTEMS
At the present time, the digital signal processing subsystems employed by complex radar systems (CRSs) are used to solve various problems. We aim to consider the digital signal processing subsystems implementing the following:
•Solution of the problems to accumulate and process information files in real time
•Information exchange between sensors and users in the course of functional problem solution
•Long-time continuous processing
•Simultaneous realizations of wide-range signal processing and control problems with relative consistency in the problems solved during the exploiting period
To satisfy the listed requirements, the microprocessor subsystems are designed for each case. In this section, we discuss the main design principles, parameters, and performance of microprocessor subsystems employed by digital signal processing subsystems in a CRS.
8.1.1 Single-Computer Subsystem
The control microprocessor (see Figure 8.1) is the central component of single-computer subsystem with the following main constituents:
•Central processor consisting of the arithmetic and logic unit (ALU) and the central control device (CCD)
•Random access memory (RAM) assigned to store information (programs, intermediate and end computations) directly used at the time of digital signal processing operations
•External memory (EM) assigned to store large information arrays for a long time and exchange with RAM by these arrays
•Input–output (I/O) devices assigned to organize the exchange of information between RAM, control microprocessor, and other facilities
•Adapters, including control console, display, and so on
In management information systems, including CRSs, a single-computer subsystem possesses some devices providing an interface between sensors and users and specific subsystems of digital signal preprocessing. In Figure 8.1, these devices are united in the same block. The control microprocessor is characterized by the total engineering data. We consider the
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I
EM
n
I/O
t
RAM
e
interface
r
f
a
ALU
c
Adapter
e
CCD
Central
processor
FIGURE 8.1 Control microprocessor.
following features of engineering data that are used only to compare the microprocessor systems between each other.
Addressness: The number of address codes used by the instruction code. There are one-, two-, three-address instructions and zero-address instructions. The control microprocessor uses the oneaddress instructions.
Number representation capacity: The control microprocessor subsystems are characterized by 16, 24, 32, and 64 digits per word.
Number representation form: There are two number representation forms: the fixed and the floating point. The control microprocessor with the fixed point represents the numbers in the form of proper fraction, and the point is fixed before the first more significant digit (MSD). The control microprocessor with floating point represents the numbers by the sign, mantissa, and order (the normal number representation form).
Microprocessor speed of operation: To characterize the speed of operation of the microprocessor subsystem, the statement of “rated speed” is introduced independently of the solved problem class in accordance with the formula
Vrs = τshort ,
(8.1)
where τshort is the duration of short operation (e.g., addition).
Effective speed of operation: The average number of operations per second for obtaining the specific digital signal processing algorithm is as follows:
Veff =
Ntotal
,
(8.2)
Tsol
where
Ntotal is the total average number of operations carried out for a single realization of digital signal processing algorithm
μis the coefficient depending on microprocessor addressness (in the case of a single-address microprocessor μ = 1)
Tsol is the time to solve the problem given by
n
Tsol = ∑Niτi
(8.3)
i=1
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where
n is the number of operation type, namely, addition, multiplication, division, addressing to RAM, and so on, carried out in the course of the digital signal processing algorithm
Ni is the number of the ith type operations
τi is the execution time of the ith type operation
Taking into consideration (8.3), we can write
Veff =
1
(8.4)
∑n
ωiτi
i=1
where ωi is the average execution frequency (probability) of the ith type operation.
Memory device size may be expressed in bit (memory cell), byte (8 bits), kbit (1024 bits), and kbyte. The memory device size may be expressed also using the computer word, that is, the number of words, a length of which in bits corresponds to the number representation capacity in microprocessor subsystem memory. Speed of operation of memory device is characterized by a memory
device cycle time τcycle. Thus, the cycle time differs between recording and reading and is defined in the following form:
τcyclerec = τsearch + τrec + τclean ;
(8.5)
τcycleread = τsearch + τread + τrebuild ,
(8.6)
where
τsearch is the time required to search information τrec is the time required to record information
τclean is the time required to clean the memory cells for preparing corresponding cells to record new information
τread is the time required to read information
τrebuild is the time required to restore information destroyed while reading
In general, the microprocessor subsystem reliability is defined by the probability of instruction issued for a correct problem solution with a single-time use of digital signal processing algorithm:
treal is the time of a single realization of digital signal processing algorithm for the solved problem
Pfail(treal) is the probability of microprocessor subsystem failure within the limits of treal, which can be rebuilt without shutting down the operation of microprocessor subsystem
Pcircuit(treal) is the probability of microprocessor subsystem circuit drop-in within the limits of treal
In the course of comparative analysis, the microprocessor subsystem’s reliability is evaluated by the average time between the microprocessor subsystem failures within the limits of treal. Here, we understand failures associated with both the hardware and the software as the failure of microprocessor subsystem.
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8.1.2 Multicomputer Subsystem
Until recently, the effective speed of operation has mainly improved due to an increase in the speed of element base operation and by designing the most efficient microprocessor subsystem functioning algorithms. At the present time, the speed of the element base operation is very close to being achieved. The use of parallel microprocessor subsystems plays a main role in increasing the effective speed of microprocessor subsystem functioning. The idea of parallel computations is very simple: several microprocessor subsystems try to solve the same problem. Technical realization of this idea depends largely on the nature of the problems to be solved (a possibility to parallel effectively a computational process) and on the level of efficacy of the modern parallel microprocessor subsystems.
One of the possible ways to increase the microprocessor subsystem performance and reliability during the digital signal processing in real time is to design and construct the multicomputer subsystems; these are used in CRSs to use effectively the digital signal processing algorithms. Computational process in the multicomputer subsystems is organized using new principles, namely, a parallel digital signal processing by several microprocessor subsystems. The main factors defining such a multicomputer subsystem structure are the end use, required performance, and memory size for the solution of the given problem in totality and functional reliability taking into consideration external environment and economical fac- tors—the maximum permissible cost and energy consumption and so on.
To provide a solution for a single target problem, we need to organize the exchange of information between the microprocessor subsystems. This operation requires adequate memory size and speed of microprocessor subsystem operation and that microprocessor subsystems be combined in computer subsystem to be used in a CRS. Another aspect is the dead time, which is caused by expectation of final solutions of some problems at the previous levels of computer subsystem. These circumstances lead to a decrease in the multicomputer subsystems’ performance compared to a single-computer subsystem’s performance. However, other parameters such as the reliability and system survival are increased essentially. Thus, we have an opportunity to exploit the digital signal processing algorithms requiring larger memory size compared to a single-microprocessor subsystem, given the structural modifications of microprocessor subsystems with limited effective speed of operation and memory size.
In general, the multicomputer subsystem performance defined by the effective speed of multicomputer subsystem operation can be given by
M
eff = K(M)∑Veff i,
(8.8)
i=1
where
Veff i is the effective operation speed of the ith microprocessor M is the number of microprocessors in the subsystem
K(M) < 1 is the coefficient taking into account the multicomputer subsystem operating costs depending on the number of microprocessors combined into a multicomputer subsystem
Microprocessors in the multicomputer subsystem may process the digital signal processing algorithms in off-line mode or while interacting with each other. In accordance with this statement, there are two types of multicomputer subsystems. The first type of multicomputer subsystems using only an information exchange between the autonomous microprocessors consist of, as a rule, the microprocessors of the same type. Each microprocessor in this multicomputer subsystem has the processor and RAM and interacts with other microprocessors through specific interface and information channels. An example of such multicomputer subsystem is the multiplexed multicomputer subsystem, in which M − m microprocessors are working and m microprocessors are redundant and M is the total number of microprocessors in the multicomputer subsystem. An important task of this
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multicomputer subsystem is to facilitate information exchange between the microprocessors. The information exchange can occur
•Between RAM of microprocessors using the common jump-address fields
•Between RAM of microprocessors using the standard information channels based on the “channel–channel” type adapters
•Between EM devices using the standard information channels based on the total EM device control
The second type of multicomputer subsystems are assigned to increase the system performance by a simultaneous solution of independent paths of parallel digital signal processing algorithm. These subsystems possess programmable structure. As a rule, the second type of multicomputer subsystems consist of the same type microprocessors or they are homogeneous. Regularized programmable communication channels that are organized using the standard information channels and switchboards carry out functional interaction between microprocessors. The switchboard and the microprocessor with a block of subsystem operation realizations (BSOR) represent the elementary cell of the homogeneous multicomputer subsystem [1–3]. Combining elementary cells in the multicomputer subsystem can be carried out by ring coupling or by routing switching. One example of the ring coupling homogeneous multicomputer subsystem is shown in Figure 8.2. Switchboards Si consist of gates opening or closing the communication channel running to a neighbor cell at the right side. BSOR consists of the adjustment register and block realizing the subsystem operations. The adjustment register content defines the switchboard function type and the degree of participation of the corresponding elementary cell while carrying out some instructions in accordance with the digital signal processing algorithm at each step. The homogeneous multicomputer subsystem operations are as follows:
•Adjustment operation assigned to program a structure of connections between the elementary cells
•Operation of information exchange assigned to organize the information exchange between the elementary cells of multicomputer subsystem
•Operation of generalized conditional jump to control a computation process during joint functioning of microprocessors in the multicomputer subsystem
•Operation of generalized unconditional jump to provide a hyphenation of computational data from one cell to other cells of the homogeneous multicomputer subsystem
The homogeneous multicomputer subsystem constructed based on these principles allows us to realize any digital signal processing algorithms. In other words, this is a universal subsystem in algorithmic sense. These homogeneous multicomputer subsystems do not have any limitations in the performance of computing complex digital signal processing algorithms and allow us to ensure the required reliability and subsystem survival in case there are unlimited number of elementary cells (microprocessors). A main task with designing homogeneous multicomputer subsystems is
S1
Si
Sn
BSOR
BSOR
BSOR
MP1
MPi
MPn
FIGURE 8.2 Ring coupling homogeneous multimicroprocessor subsystem.
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to define the number of elementary cells, which ensures the realization of complex digital signal processing algorithms in real time and required operational reliability taking into consideration the multicomputer subsystem losses in the effective speed of operations.
8.1.3 Multimicroprocessor Subsystems for Digital Signal Processing
Computer subsystem consisting of several microprocessors coupled with each other by the common RAM and interface is called the multimicroprocessor subsystem. As a rule, the multimicroprocessor subsystem is designed based on the homogeneous single-microprocessor subsystems. Homogeneity ensures their interchangeability that allows us to increase efficiently the reliability and survival of the multimicroprocessor subsystem. The presence of common RAM that is equally available for all microprocessors reduces costs of the multimicroprocessor subsystem, which are required for data exchange in the course of parallel computation. The multimicroprocessor subsystem performance increases compared to the single-microprocessor subsystem due to simultaneous digital signal processing of several problems or parallel digital signal processing of some parts of the same problem. To use effectively the multimicroprocessor subsystem we need to separate a whole set of problems that must be solved on a set of subprograms that can be used in parallel and, in this case, the information delivered from the same RAM. In this case, a computational ganging is carried out by the unified control instruction stream for all microprocessors compared to the multicomputer subsystems. The multimicroprocessor subsystem programming differs from the multicomputer subsystem one and is a specific problem associated with systems programming theory and technique.
At the present time, the homogeneous multimicroprocessor subsystems for digital signal processing are designed based on two structural types: in the case of parallel digital signal processing—the matrix and associative structure, and in the case of sequential digital signal processing—the backbone structure. The matrix of homogeneous multimicroprocessor subsystems possess a single control block (CB) and a set of microprocessors combined into a matrix form (see Figure 8.3). Each microprocessor has its own RAM and operates with internal data, and the multimicroprocessor subsystem operates with larger arrayed data. There are the central control block (CCB) and memory device that store the data and programs in the homogeneous multimicroprocessor subsystem structure. In addition, the common memory may be included in the homogeneous multimicroprocessor subsystem structure
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and all microprocessors are able to address the common memory following the assigned regulations. Description of the matrix homogeneous multimicroprocessor systems is widely presented in literature [4–8]. Associative parallel homogeneous multimicroprocessor subsystems differ from the matrix ones by the presence of the so-called associative memory, that is, the memory where the data are selected based on the data content, not data address. The homogeneous multimicroprocessor subsystems with parallel structure are assigned to solve the problems possessing a natural parallelism [9] since all microprocessors of this system carry out the same operation simultaneously (each microprocessor uses its own data). These subsystems can be used in CRSs used for digital signal processing operations, including spatial-time signal processing, filtering of the target trajectory parameters by recurrent filters realized in the matrix form, and others where the linear algebra operations must be done, for example, the multiplication of vectors and matrices, the matrix inversion, and so on.
The backbone multimicroprocessor subsystem combines several independent microprocessors coupled with each other in such a way that information at the output of one microprocessor comes in at the input of another microprocessor; that is, the microprocessors process information sequentially or in conveyer style. The conveyer style of digital signal processing is based on partition of the digital signal processing algorithm on a set of steps and matching in time these steps when the digital signal processing algorithm is accomplished. Advantages with implementing the backbone multimicroprocessor subsystems compared to the matrix homogeneous multimicroprocessor ones are the moderate requirements with respect to inner coupling and the simplicity with which the backbone multimicroprocessor subsystem’s computational power can be increased. Further disadvantages are removed by organizing priority exchange of information between the system cells.
Two types of backbone multimicroprocessor subsystems are widely used for digital signal processing in real time [10–12]: The first type is a one-dimensional inner long-distance channel operating in the time-sharing mode (see Figure 8.4), and the second type is a multidimensional inner long-distance channel coupled with two-input RAM, in particular (see Figure 8.5). In the backbone multimicroprocessor subsystem of the first kind, all RAM and read-only memory (ROM), central microprocessor (CMP), and specific microprocessors (SMPs) are coupled by the same channel. There is a block to control the channel. This block is used in the case of conflicts when several microprocessors address RAM simultaneously and for controlling data upload and extraction using the channel units to exchange data.
ROM
RAM
Channel
control
CMP
I/O
SMP
device
FIGURE 8.4 Backbone multimicroprocessor subsystem with a single inner long-distance channel.
CMP1
CMP2
RAM1
RAMn
RAM1
RAMn
Channels
SMP
FIGURE 8.5 Backbone multimicroprocessor subsystem with multidimensional inner long-distance channel.
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Operation of a single backbone multimicroprocessor subsystem is carried out in the following way. Each microprocessor submits, as needed, an application to the channel to address to RAM or ROM. If the channel is free then the microprocessor can access RAM or ROM immediately. Otherwise, the microprocessor is in the idle mode. The microprocessor can access RAM or ROM when the previous queries from other microprocessors are ended and there is no query from the microprocessors with high priority. Consequently, there are high requirements of the information channel with respect to the data throughput. Determination of the required throughput is carried out for each specific case, using the queuing theory methods. Note that the mentioned structure of the backbone multimicroprocessor subsystem has a limited speed of operation defined by the data channel throughput and, in addition, with the data channel failure the backbone multimicroprocessor subsystem stops any operation. A great advantage of the backbone multimicroprocessor subsystem is its simplicity.
In the backbone multimicroprocessor subsystem with the multidimensional inner long-distance channel (see Figure 8.5) all microprocessors operate using the independent asynchronous mode and all conflict situations are practically excluded. This system has high reliability and allows us to increase the performance without any limitations. Disadvantage of the backbone multimicroprocessor subsystem with the multidimensional inner long-distance channel is the high complexity caused by the multiinput RAM and ROM use. While designing the multimicroprocessor subsystem, the main problem is to provide the required performance by selecting the number of microprocessors to be included in this subsystem. With an increase in the number of microprocessors in the multimicroprocessor subsystem structure, a portion of overhead caused by a waiting time while the microprocessor addresses RAM or ROM and simultaneously addressing common tables and operational systems also causes an increase in the timetables related to supervisory routing. The total performance of multimicroprocessor subsystem is determined in the following form:
′
− η),
(8.9)
= MVeff (1
where
V ′ is the effective speed of operation of a single microprocessor
eff
η is the coefficient of relative performance loss
Equation 8.9 allows us to define approximately the required number of microprocessors if the required total multimicroprocessor subsystem performance is defined in advance.
8.1.4 Microprocessor Subsystems for Digital Signal Processing in Radar
The microcomputer constructed based on a microprocessor possess high reliability and flexible universality; however, speed of operation is low. In this case, the required performance in the course of the digital signal processing in a CRS can be reached by multiple microcomputer systems using several microprocessors. Such computer systems are called the microprocessor systems. Any such microprocessor subsystem has a network facilitating communication between the elements of microprocessor subsystem for data exchange between the microcomputers. Configuration and level of complexity of such communications depend on digital signal processing algorithms used by CRSs, distribution of operations between the microcomputers, and the acceptable number of RAM used by one microcomputer.
For an example, consider the microprocessor subsystem block diagram presented in Figure 8.6. The main element of this microprocessor subsystem is the microcomputer consisting of the microprocessor, RAM, I/O interface, and switchboard providing communication between the microcomputer elements and other elements of the microprocessor subsystem. Total memory of the microprocessor subsystem is based on the RAM added to the microcomputer. Each microprocessor is able to address the local RAM or RAM of other microcomputers by means of the address translation controller (ATC). The process of any microprocessor addressing the microprocessor subsystem’s total memory is facilitated
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ATC1
ATC2
ATC3
MC
MC
MC
MC
MC
MC
MC
MC
MP
S
I/O
RAM interface
Microcomputer—MC
FIGURE 8.6 Example of microprocessor subsystem.
in such ways. Addressing mechanism is absolutely independent of RAM topology in the microprocessor subsystem. Access time is a function of distance to the addressed RAM cell. Communication of microcomputers with ATC is carried out by the one-channel data bus in the time-sharing mode. In doing so, we assume that the microprocessor will address mainly the local RAM; that is, the microprocessor will not use the data bus between microcomputers. However, to ensure the required reliability of the microprocessor subsystem and the possibility to increase it, the microcomputers are coupled into blocks consisting of 1–14 microcomputers.
The considered microprocessor subsystem structure possesses a high level of complexity of communication between the microprocessor and RAM, which leads to losses in the effective speed of operation. The high performance can be reached only when there is high efficiency of interaction between the microcomputers. In particular, the data bus overloading should be prevented. For this purpose, we need to ensure that, on priority, each microprocessor addresses local RAM in the course of the parallel digital signal processing. Another example of the microprocessor subsystem is depicted in Figure 8.7. In this microprocessor subsystem, an asynchronous communication between the microcomputers and RAM is used. If several microprocessors are coupled to the data bus they work using the time-sharing mode. Operational efficacy depends on channel throughput.
MP11
MP12
MP13
Data bus
RAM
MP21
MP22
Data bus
RAM
MP31
MP32
Data bus
FIGURE 8.7 Example of microprocessor subsystem.
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For unloading the data bus, the local RAM is introduced to each microcomputer accessible for addressing by the given microprocessor. Thus, by using the data bus it is possible for other microprocessors coupled to the data bus to access the RAM. Integration of several one-channel data bus into a single data bus is possible.
8.2 REQUIREMENTS FOR EFFECTIVE SPEED OF OPERATION
Digital signal processing in CRSs is carried out in real time depending on the speed of incoming requests to realize the definite signal processing algorithms. These requests would be satisfied by a CRS within the limited time period defined by the speed of incoming requests from corresponding stages of the digital signal processing algorithms. Consequently, the main problem with designing the microprocessor subsystems is to satisfy the main limitations during attended time of requests coming into the microprocessor subsystem. A favorable basis for studying the microprocessor subsystem operation in dynamical mode, in order to define the main requirements to structure and technical parameters, is the queuing theory [13]. In this section, we define the main specifications of the microprocessor subsystems employed by CRSs with respect to the speed of operation during digital signal processing in real time.
8.2.1 Microprocessor Subsystem as a Queuing System
The queuing system (QS) interacts with sources of requests for queuing. In the discussed case, the targets and other interferences in the radar coverage are considered as the sources of queuing requests (see Figure 8.8). These sources interact with the QS through the request sensor—the CRS plays this role. The radar system transforms the queuing request into signals that are subjected to process. Time sequence of these signals, which is ordered during radar sensing and scanning of the controlled space, forms an input request flux for the QS.
In general, the input request flux is considered as a stochastic process given by the probability density function of interval duration between the instants of two neighboring requests. The initial input flux of requests for a CRS is the target set in the radar coverage. At the initial designing stage, we can think that pdf of time intervals τtg between the neighboring targets is given by the exponential function:
MP
MP
MP
MP
MP
MP
MP
MP
MP
