Diss / 10

Ptr

FIGURE 7.10  Typical graph of target and target pip identification algorithm.

Now, we can determine the work content of the elementary DSP algorithms a1,…, a10 including into the complex digital signal reprocessing algorithm presented in Figure 7.7. At first, we consider the typical algorithm of target pip and track identification presented by the graph tops a2, a5, a8. For this purpose, we present this algorithm in the graph form shown in Figure 7.10. The elementary DSP algorithms (operators) are the following:

1.Selection of the next target pip (or target track parameters) from the corresponding scanned area (the algorithm a1, Figure 7.10).

2. Computation | t − t − | ≤ tacceptable (the algorithm a , Figure 7.10). A sense of this opera-

n n 1 n 2

tion is the following: is it a new or old target track? The work content of this operation is equal to m2 = 2 of the reduced arithmetical operations.

3.If the condition 2 is satisfied, a verification of new target pip hit to the gate formed around the extrapolated point of selected target track is carried out. This verification is carried out by several stages. At first, the verification is made by the coordinate x

(the algorithm a3), after that by the coordinate y (the algorithm a4), and finally, by the coordinate z (the algorithm a5) under the condition that tests using the previous coordinates give us a positive result. If at the regular step the conditions are not satisfied,

we should follow by the algorithm a6, that is, to verify the fact that all target tracks of scanned area have been tested. If “No,” we must carry out a transition to the algorithm

a1; if “Yes,” we should make identification with the next set of target tracks (the output algorithm).

Operations carried out under identification by a single coordinate independently of identified target track kind are the following:

1. Extrapolation of the selected target track coordinate by the formula

2. Computation of the extrapolation error variance by the following formula:

254 Signal Processing in Radar Systems

Elementary calculations show that under comparison by a single coordinate in accordance with the given formula, there is a need to explore 35 reduced arithmetical operations. Consequently, m3 = m4 = m5 = 35. Under definition of the probabilities Pij in the network graph presented in Figure 7.10, we assume the following:

1.The number of cancelled target tracks owing to old information does not exceed 1% from

the total number of tracking targets. In accordance with this principle, we have P23 = 0.99; P26 = 0.01.

2.For 95% cases, the identification process is finished after comparison by one coordinate. Because of this, P36 = 0.95; P34 = 0.05.

3.The probabilities of identification by two and three coordinates are so small that we can neglect these probabilities under determination of the work content of complex DSP algorithm. Under computation of the identification algorithm work content, we are able to obtain, individually by each target track array, the following parameters:

a.The minimal work content corresponding to the case when the new target pip is within the limits of the first selected target track gate; the number of reduced arithmetical operations independent of the array equals to

b.The maximal work content corresponding to the case when the new target pip is assigned for identification with target tracks of next array after unsuccessful identification with target tracks of the current array; the number of the reduced arithmetical operations for the array of tracking target tracks is given by

In the case of other arrays, we have

The average work content can be determined in the following form:

To simplify further computation, we transform a sequent graph in Figure 7.7 into a parallel graph depicted in Figure 7.11. For this parallel graph, the probabilities of transitions to the graph tops

In the case of linear target track, that is, s = 1 and n = 3, we have M6 ≈ 400 reduced arithmetical operations.

5.The work contents of the algorithm a7 fixing the fact of target track detection and controlling the rerecording of detected target track array to the array of target tracking

trajectories, the algorithm a9 carrying out the estimation of initial magnitudes of initial magnitudes of target track parameters and transferring this estimation to the array of

detected target tracks, and the algorithm a10 carrying out a record of target pips as an initial coordinate point of new target tracks can be neglected at this stage owing to simplicity of their realization.

Now, we can determine the average work content of complex DSP algorithm as a whole

M = M1 + Ptr (M2 + M3 + M4 ) + PD (M5 + M6 + M7 ) + Pbeg (M8 + M9 ) + Pnew (M10 + M11). (7.47)

Substituting in (7.47) the values obtained before, we obtain M ≈ 6700. Henceforth, there is a need to take into consideration no arithmetical operations by the corresponding coefficient of reduction Kredna . For example, let Kredna = 3. Then, we obtain that the total number of operations required for microprocessor subsystem in the case of a single realization of the considered complex digital signal reprocessing can be presented as M ≈ 2 × 104 operations. Thus, in the considered example, there is a need to use 2 × 104 microprocessor operations on average to process a single target pip. Naturally, this number corresponds only to the considered algorithm and can be reduced significantly if we are able to upgrade the algorithm of target pip identification, to simplify the algorithm of target track parameters smoothing, etc. The main purpose of consideration of this example is to present a possibility to calculate the work content of the complex DSP algorithm and indicate simultaneously some problems arising in the course of these calculations.

7.4  PARALLELING OF COMPUTATIONAL PROCESS

The results of work content evaluation of the complex DSP algorithm give us the initial information to select the structure and elements of microprocessor subsystems assigned to realize this complex DSP algorithm in a CRS. To ensure the required work content and operational reliability, the designed computational subsystem must include several microprocessor subsystems, as a rule. The main peculiarity of these subsystems is instrument or programmable parallelism of the computational­ process. To organize the parallel computational process, there is a need to carry out a paralleling of the complex DSP algorithm. In a general case, the paralleling of the complex DSP algorithms can be considered only for a specific problem taking into consideration the supposed structure of the computational system. Consequently, in the course of designing, the problems of selecting a structure of computational system based on the microprocessor subsystems and algorithmic transformation in accordance with the proposed structure of computational system are closely related. There is a set of general statements and methods of algorithmic solution paralleling, and we consider some of these methods in this section.

7.4.1  Multilevel Graph of Complex Digital Signal Processing Algorithm

The source for paralleling is the graph flowchart of algorithm presented in the multilevel form [8]. The multilevel form is introduced as a generalization of graph flowcharts to illustrate possibilities of serial–parallel operation of algorithms and is a characteristic of the fact that the tops of each level are not related by information features since the final results of operations carried out by one top cannot be considered as initial data for another top. Operations of independent tops (algorithms) can be performed simultaneously. Consequently, there is a possibility to realize the elementary DSP algorithms at the definite level using different microprocessor subsystems.

FIGURE 7.12  Multilevel graph of complex DSP algorithm.

The multilevel graph form is obtained in the following way (see Figure 7.12). The first-level top is called the top that has no input arc. The second-level top is the top whose input arc is the output arc of the first-level top. By analogous way, the (n − 1)th level top is the top whose input arc is the output arc of the nth-level top and the output arcs of some previous level tops. In the realization of elementary DSP algorithms, a paralleling is also possible based on the network graph representation of the complex DSP algorithm for the solved problem. In this case, we should transform the initial graph form to the multilevel one. In the case of multilevel graph form, each level represents independent elementary DSP algorithms or their set, one of which is carried out necessarily in the course of a single realization of the complex DSP algorithm. If an individual microprocessor subsystem is used to realize the elementary DSP algorithms of each level, we obtain the so-called pipeline subsystem, in which several operations are made simultaneously on data passing in sequence. In this case, the DSP is divided into several stages (by the number of graph levels) and each stage is carried out in parallel with other stages.

To evaluate possibilities of parallel computation organization based on the multilevel algorithmic

graph, we introduce a set of quantitative characteristics, namely, bi is the ith level width, that is, the number of independent branches at the ith level; B is the width of the multilevel graph or

max{bi}; L is the graph length, that is, maximal critical way leading from zero to the final state,

i

and so on. As follows from the multilevel graph, the realization time of a set of DSP algorithms is limited by some threshold value Tth. By knowing Tth, we can evaluate the required number of the same type of microprocessors Nmp to realize the given set of elementary DSP algorithms. In doing so, we obtain

where

m

Tmpsingle = ∑i=1 ti is the realization time of all algorithms for a single microprocessor subsystem

ti is the realization time of the ith elementary DSP algorithm

m is the number of elementary DSP algorithms in the complex one

We consider a design procedure of the multilevel graph using an example of algorithm paralleling for the linear recurrent filtering of target track parameters given by the state equation (5.1). In the given case, the linear recurrent filtering algorithm takes the following form:

where

ˆ

θn is the (s × 1) vector of estimated target track parameters

qˆ exn is the (s × 1) vector of extrapolated target track parameters Yn is the (m × 1) vector of measured coordinate magnitudes Yˆ exn is the (m × 1) vector of extrapolated coordinate magnitudes

ηn−1 is the (h × 1) vector of disturbance of target track parameters Φn is the transfer (s × s) matrix of target track model

Ψn is the correlation (s × s) matrix of errors of target track parameter estimation Yexn is the correlation (s × s) matrix of extrapolation of target track parameters Ψη is the correlation (h × h) matrix of target track random disturbances

Γn is the (s × h) matrix (see (5.1)) Hn is the (m × s) matrix (see (5.11))

Rn is the correlation (m × m) error matrix of target track coordinate measurements

Dimensions of matrices and vectors are required in determination of the work content for the branches of the multilevel complex DSP algorithm graph.

The ordinary complex DSP algorithm graph is the basis for the multilevel graph. In the case of ordinary complex DSP algorithm graph, the two-input functional operators on vector and matrices are considered as the tops and results of operations, and transitions in the graph are considered as the arcs. In doing so, a set of arcs without initial tops is an ensemble of initial arguments, and a totality of arcs without the end tops is a set of output results. The graph, as a rule, is designed manually because to formalize this process is a very difficult problem. The initial graph of linear filtering algorithm is depicted in Figure 7.13. To design the multilevel graph, at first, we should present the initial graph in the form of adjacency matrix with the number of columns and rows equal to the number of initial graph tops. The elements of the adjacency matrix lij take the value 0 if there is no arc between the top i and the top j and the value 1 if there is an arc between the top i and the top j. The adjacency matrix elements of the multilevel graph shown in Figure 7.13 are represented in Table 7.2.

The transformation process of the initial complex DSP algorithm graph into the multilevel complex DSP algorithm graph is to sort the adjacency matrix rows and columns and is based on an adjacency matrix feature to have zero rows if there are end tops and zero columns if there are initial tops, that is, all arcs for these tops are initial. In our case, the tops “1,” “2,” “8,” and “10” are the initial tops. These tops form the first level of the sorted multilevel graph. The next step is nulling all the nonzero elements of rows with the numbers selected at the first step. At the same time, the first level tops are considered as the end tops and the output arcs are considered as the input arcs for the

FIGURE 7.13  The multilevel graph of linear filtering algorithm.

TABLE 7.2

Adjacency Matrix Elements of the Multilevel Graph Shown in Figure 7.13

262 Signal Processing in Radar Systems

TABLE 7.4

Distribution of Graph Tops along the Levels

FIGURE 7.15  Multilevel graph.

simultaneously under realization of the linear filtering algorithm. Consequently, several microprocessor subsystems, namely, from 1 to 3, respectively, can participate in the computational process. In doing so, the realization time of the complex DSP algorithm can be reduced essentially, since instead of 20 macro-operations carried out in sequence by one microprocessor subsystem there is a need to carry out not more than 10 macro-operations for each microprocessor subsystem in parallel scheme.

Further transformations of the multilevel graphs can be carried out in two avenues: (a) definition of rational number of microprocessor subsystems realizing the paralleling complex DSP algorithm within the limits of the given minimal time and (b) optimal distribution of macro-operations by microprocessor subsystems if the number of microprocessor subsystems is given and their characteristics are known and the minimal realization time is a criterion of effectiveness. To solve both the first and the second problems, there is a need to obtain additional information concerning the weights of graph tops, that is, the number of elementary operations carried out during a realization of all macro-operations, by which the graph tops are marked.