17.3TIM1 time base unit

The timer has a time base unit that includes:

●16-bit up/down counter

●16-bit auto-reload register

●Repetition counter

●Prescaler

Figure 32. Time base unit

Legend:

event interrupt

The 16-bit counter, the prescaler, the auto-reload register and the repetition counter register can be written or read by software.

The auto-reload register is composed of a preload register plus a shadow register.

Writing to the auto-reload register can be done in two modes:

●Auto-reload preload enabled (ARPE bit set in the TIM1_CR1 register). In this mode, when data is written to the auto-reload register, it is kept in the preload register and transferred into the shadow register at the next update event (UEV).

●Auto-reload preload disabled (ARPE bit cleared in the TIM1_CR1 register). In this mode, when data is written to the auto-reload register it is transferred into the shadow register immediately.

17.3.1Reading and writing to the 16-bit counter

There is no buffering when writing to the counter. Both TIM1_CNTRH and TIM1_CNTRL can be written at any time, so it is suggested not to write a new value into the counter while it is running to avoid loading an incorrect intermediate content.

An 8-bit buffer is implemented for the read. Software must read the MS byte first, after which the LS byte value is buffered automatically (see Figure 33). This buffered value remains unchanged until the 16-bit read sequence is completed.

17.3.2Write sequence for 16-bit TIM1_ARR register

16-bit values are loaded in the TIM1_ARR register through preload registers. This must be performed by two write instructions, one for each byte. The MS byte must be written first.

The shadow register update is blocked as soon as the MS byte has been written, and stays blocked until the LS byte has been written. Do not use the LDW instruction as this writes the LS byte first which produces incorrect results.

17.3.3Prescaler

The prescaler implementation is as follows:

The TIM1 prescaler is based on a 16-bit counter controlled through a 16-bit register (in TIM1_PSCR register). It can be changed on the fly as this control register is buffered. It can divide the counter clock frequency by any factor between 1 and 65536.

The counter clock frequency is calculated as follows:

fCK_CNT = fCK_PSC/(PSCR[15:0]+1)

The prescaler value is loaded through a preload register. The shadow register, which contains the current value to be used, is loaded as soon as the LS byte has been written.

To update the 16-bit prescaler, load two bytes in separate write operations starting with the MSB. Do not use the LDW instruction for this purpose as it writes the LSB first.

The new prescaler value is taken into account in the following period (after the next counter update event).

Read operations to the TIM1_PSCR registers access the preload registers, so no special care needs to be taken to read them.

17.3.4Up-counting mode

In up-counting mode, the counter counts from 0 to a user-defined compare value (content of the TIM1_ARR register). It then restarts from 0 and generates a counter overflow event and a UEV if the UDIS bit is 0 in the TIM1_CR1 register.

Figure 34 shows an example of this counting mode.

Figure 34. Counter in up-counting mode

An update event can also be generated by setting the UG bit in the TIM1_EGR register (either by software or by using the trigger controller).

The UEV can be disabled by software by setting the UDIS bit in the TIM1_CR1 register. This is to avoid updating the shadow registers while writing new values in the preload registers. No UEV occurs until the UDIS bit has been written to 0. Note that the counter and the prescaler restart counting from 0 but, the prescaler division factor does not change. In addition, if the URS bit (update request selection) in the TIM1_CR1 register is set, setting the UG bit generates an UEV without setting the UIF flag. Consequently, no interrupt request is sent. This avoids generating both update and capture interrupts when clearing the counter on the capture event.

When an update event occurs, all the registers are updated and the update flag (UIF bit in TIM1_SR1 register) is set (depending on the URS bit):

●The auto-reload shadow register is updated with the preload value (TIM1_ARR).

●The buffer of the prescaler is reloaded with the preload value (content of the TIM1_PSCR register).

Figure 35 and Figure 36 show two examples of the counter behavior for different clock frequencies when TIM1_ARR = 0x36.

In Figure 35, the prescaler divider is set to 2, so the counter clock (CK_CNT) frequency is at half the frequency of the prescaler clock source (CK_PSC). The auto-reload preload is disabled (ARPE = 0). Consequently, the shadow register is immediately changed and counter overflow occurs when upcounting reaches 0x36. This generates a UEV.

Figure 35. Counter update when ARPE = 0 (ARR not preloaded) with prescaler = 2

In Figure 36 the prescaler divider is set to 1, so CK_CNT has the same frequency as CK_PSC. The auto-reload preload is enabled (ARPE = 1), so the next counter overflow occurs at 0xFF. The new auto-reload value register value of 36h is taken into account after the overflow which generates a UEV.

Figure 36. Counter update event when ARPE = 1 (TIM1_ARR preloaded)

New value transferred in shadow register on counter overflow