When checking this time-out, the slave node is desynchronized for the reception of the LIN Break and Synch fields. Consequently, a margin must be allowed, taking into account the worst case: This occurs when the LIN identifier lasts exactly 10 TBIT_MASTER periods. In this case, the LIN Break and Synch fields last 49 - 10 = 39 TBIT_MASTER periods.

Assuming the slave measures these first 39 bits with a desynchronized clock of 15.5%. This leads to a maximum allowed Header Length of:

39 x (1/0.845) TBIT_MASTER + 10 TBIT_MASTER

= 56.15 TBIT_SLAVE

A margin is provided so that the time-out occurs when the header length is greater than 57 TBIT_SLAVE periods. If it is less than or equal to 57 TBIT_SLAVE periods, then no time-out occurs.

Mute mode and errors

In mute mode, if an LHE error occurs during the analysis of the LIN Synch Field or if a LIN Header Time-out occurs then the LHE bit is set but it does not wake up from mute mode. In this case, the current header analysis is discarded. If needed, the software has to reset the LSF bit. Then the UART searches for a new LIN header.

In mute mode, if a framing error occurs on a data (which is not a break), it is discarded and the FE bit is not set.

Any LIN header which respects the following conditions causes a wake-up from mute mode:

●A valid LIN Break and Delimiter

●A valid LIN Synch Field (without deviation error)

●A LIN Identifier Field without framing error. Note that a LIN parity error on the LIN Identifier Field does not prevent wake-up from mute mode.

●No LIN Header Time-out should occur during Header reception.

22.4.3Slave mode with automatic resynchronization enabled

Automatic resynchronization

When automatic resynchronization is enabled, after each LIN Break, the time duration

between 5 falling edges on RDI is sampled on fMASTER and the result of this measurement is stored in an internal 19-bit register called SM (not user accessible) (See Figure 135).

Then the UARTDIV value (and its associated BRR1 and BRR2 registers) are automatically updated at the end of the fifth falling edge. During LIN Synch field measurement, the UART state machine is stopped and no data is transferred to the data register.

Figure 135. LIN synch field measurement

UARTDIV is an unsigned integer, coded in the BRR1 and BRR2 registers as shown in

Figure 119.

If LASE bit = 1 then UARTDIV is automatically updated at the end of each LIN Synch Field.

Three registers are used internally to manage the auto-update of the LIN divider (UARTDIV):

●UARTDIV_NOM (nominal value written by software at UART_BRR1 and UART_BRR2 addresses)

●UARTDIV_MEAS (results of the Field Synch measurement)

●UARTDIV (used to generate the local baud rate)

The control and interactions of these registers are explained in Figure 136 and Figure 137. They depend on the LDUM bit setting (LIN Divider Update Method)

As explained in Figure 136 and Figure 137, UARTDIV can be updated by two concurrent actions: a transfer from UARTDIV_MEAS at the end of the LIN Sync Field and a transfer from UARTDIV_NOM due to a software write to BRR1. If both operations occur at the same time, the transfer from UARTDIV_NOM has priority.

Figure 136. UARTDIV read / write operations when LDUM = 0

Deviation error on the synch field

The deviation error is checked by comparing the current baud rate (relative to the slave oscillator) with the received LIN Synch Field (relative to the master oscillator). Two checks are performed in parallel.

The first check is based on a measurement between the first falling edge and the last falling edge of the Synch Field.

●If D1 > 14.84% LHE is set

●If D1< 14.06% LHE is not set

●If 14.06% < D1 < 14.84% LHE can be either set or reset depending on the dephasing between the signal on UART_RX pin and the fMASTER clock

The second check is based on a measurement of time between each falling edge of the Synch Field

●If D2 > 18.75% LHE is set

●If D2 < 15.62% LHE is not set

●If 15.62% < D2 < 18.75% LHE can be either set or reset depending on dephasing between the signal on UART_RX pin and the fMASTER clock

Note that the UART does not need to check if the next edge occurs slower than expected. This is covered by the check for deviation error on the full synch byte.

If LDUM bit is set, the next character reception will automatically reload the baudrate generator with nominal value.

You can also reload the nominal value by writing to BRR2 and BRR1. This second method is typically used when an error occurs during response transmission or reception.

If for any reason, the LDUM bit is set when UART is receiving a new Break and a Synch Field, this bit will be ignored and cleared. UART will adjust the baudrate generator with a value calculated from the synch field.

LIN header error detection

LHE is set if one of the following conditions occurs:

●Break Delimiter is too short

●Deviation error on the Synch Field is outside the LIN specification which allows up to +/ -14% of period deviation between the slave and master oscillators.

●Framing error in Synch Field or Identifier Field

●A LIN header reception time-out

●An overflow during the Synch Field Measurement, which leads to an overflow of the divider registers

LIN header time-out error

The description in the section LIN header time-out error on page 340 applies also when automatic resynchronization is enabled.

UART clock tolerance when synchronized

When synchronization has been performed, following reception of a LIN Break, the UART has the same clock deviation tolerance as in UART mode, which is explained below:

During reception, each bit is oversampled 16 times. The mean of the 8th, 9th and 10th samples is considered as the bit value.

Consequently, the clock frequency should not vary more than 6/16 (37.5%) within one bit.

The sampling clock is resynchronized at each start bit, so that when receiving 10 bits (one start bit, 1 data byte, 1 stop bit), the clock deviation should not exceed 3.75%.

UART clock tolerance when unsynchronized

When LIN slaves are unsynchronized (meaning no characters have been transmitted for a relatively long time), the maximum tolerated deviation of the UART clock is +/-14%.

If the deviation is within this range then the LIN Break is detected properly when a new reception occurs.

This is made possible by the fact that masters send 13 low bits for the LIN Break, which can be interpreted as 11 low bits (13 bits -14% = 11.18) by a "fast" slave and then considered as a LIN Break. According to the LIN specification, a LIN Break is valid when its duration is greater than tSBRKTS = 10. This means that the LIN Break must last at least 11 low bits.

If the period desynchronization of the slave is +14% (slave too slow), the character "00h" which represents a sequence of 9 low bits must not be interpreted as a break character (9 bits + 14% = 10.26). Consequently, a valid LIN break must last at least 11 low bits.

Clock deviation causes

The causes which contribute to the total deviation are:

●DTRA: Deviation due to transmitter error. Note: the transmitter can be either a master or a slave (in case of a slave listening to the response of another slave).

●DMEAS: Error due to the LIN Synch measurement performed by the receiver.

●DQUANT: Error due to the baud rate quantization of the receiver.

●DREC: Deviation of the local oscillator of the receiver: This deviation can occur during the reception of one complete LIN message assuming that the deviation has been compensated at the beginning of the message.

●DTCL: Deviation due to the transmission line (generally due to the transceivers)

●All the deviations of the system should be added and compared to the UART clock tolerance:

– DTRA + DMEAS+ DQUANT + DREC + DTCL < 3.75%

Error due to LIN synch measurement

The LIN Synch Field is measured over eight bit times.

This measurement is performed using a counter clocked by the CPU clock. The edge detections are performed using the CPU clock cycle.

This leads to a precision of 2 CPU clock cycles for the measurement which lasts 8*UARTDIV clock cycles.

Consequently, this error (DMEAS) is equal to:

2 / (8*UARTDIVMIN)

UARTDIVMIN corresponds to the minimum LIN prescaler content, leading to the maximum baud rate, taking into account the maximum deviation of +/-14%.

Error due to baud rate quantization

The baud rate can be adjusted in steps of 1 / (UARTDIV). The worst case occurs when the "real" baud rate is in the middle of the step.

This leads to a quantization error (DQUANT) equal to 1 / (2*UARTDIVMIN).