
- •ADSP-2192M DUAL CORE DSP FEATURES
- •FUNCTIONAL BLOCK DIAGRAM
- •DSP CORE FEATURES
- •TABLE OF CONTENTS
- •GENERAL DESCRIPTION
- •Figure 1. ADSP-219x DSP Core
- •DSP Core Architecture
- •DSP Peripherals
- •Memory Architecture
- •Figure 2. ADSP-2192M Internal/External Memory, Boot Memory, and I/O Memory Maps
- •Interrupts
- •DMA Controller
- •External Interfaces
- •PCI 2.2 Host Interface
- •USB 1.1 Host Interface
- •Sub-ISA Interface
- •CardBus Interface
- •AC’97 2.1 External Codec Interface
- •Serial EEPROM Interface
- •Internal Interfaces
- •Register Interface
- •Register Spaces
- •PCI Configuration Space
- •DSP Core Register Space
- •Peripheral Device Control Register Space
- •USB Register Space
- •CardBus Interface
- •Using the PCI Interface
- •Target/Slave Interface
- •Bus Master Interface
- •PCI Interrupts
- •PCI Control Register.
- •PCI Configuration Space
- •Similarities Between the Three PCI Functions
- •Interactions Between the Three PCI Configurations
- •PCI Memory Map
- •Figure 3. PCI Addressing for 24-Bit and 16-Bit Memory Blocks in 24-Bit Access (BAR2) Mode
- •Figure 4. PCI Addressing for 24-Bit and 16-Bit Memory Blocks in 16-Bit Access (BAR3) Mode
- •24-Bit PCI DSP Memory Map (BAR2)
- •16-Bit PCI DSP Memory Map (BAR3)
- •16-Bit PCI DSP I/O Memory Map (BAR4)
- •Using the USB Interface
- •USB DSP Register Definitions
- •USB DSP Memory Buffer Base Addr Register
- •USB DSP Memory Buffer Size Register
- •USB DSP Memory Buffer RD Pointer Offset Register
- •USB DSP Memory Buffer WR Pointer Offset Register
- •USB Descriptor Vendor ID
- •USB Descriptor Product ID
- •USB Descriptor Release Number
- •USB Descriptor Device Attributes
- •USB DSP MCU Register Definitions
- •USB Endpoint Description Register
- •USB Endpoint NAK Counter Register
- •USB Endpoint Stall Policy Register
- •USB Endpoint 1 Code Download Base Address Register
- •USB Endpoint 2 Code Download Base Address Register
- •USB Endpoint 3 Code Download Base Address Register
- •USB Endpoint 1 Code Current Write Pointer Offset Register
- •USB Endpoint 2 Code Current Write Pointer Offset Register
- •USB Endpoint 3 Code Current Write Pointer Offset Register
- •USB SETUP Token Command Register
- •USB SETUP Token Data Register
- •USB SETUP Counter Register
- •USB Register I/O Address Register
- •USB Register I/O Data Register
- •USB Control Register
- •USB Address/Endpoint Register
- •USB Frame Number Register
- •General USB Device Definitions
- •Configuration 0, 1, and 2 Device Definition
- •Endpoint 0 Definition
- •USB MCU Code Download
- •USB REGIO (Write)
- •USB REGIO (Read)
- •DSP Code Download
- •Example Initialization Process
- •USB Data Pipe Operations
- •OUT Transactions (Host to Device)
- •IN Transactions (Device to Host)
- •Sub-ISA Interface
- •PCI Interface to DSP Memory
- •USB Interface to DSP Memory
- •AC’97 Codec Interface to DSP Memory
- •Data FIFO Architecture
- •FIFO Control Registers
- •System Reset Description
- •Power-On Reset
- •DSP Software Reset
- •Booting Modes
- •Figure 5. Boot Process Flow
- •Power Management Description
- •Power Regulators
- •Low Power Operation
- •Clock Signals
- •Figure 7. External Crystal Connections
- •Figure 8. Clock Domains
- •Instruction Set Description
- •Development Tools
- •Designing an Emulator-Compatible DSP Board (Target)
- •Target Board Header
- •Figure 9. JTAG Target Board Connector for JTAG Equipped Analog Devices DSP (Jumpers in Place)
- •Figure 10. JTAG Target Board Connector with No Local Boundary Scan
- •JTAG Emulator Pod Connector
- •Figure 11. JTAG Pod Connector Dimensions
- •Figure 12. JTAG Pod Connector Keep-Out Area
- •Design-for-Emulation Circuit Information
- •Additional Information
- •PIN DESCRIPTIONS
- •SPECIFICATIONS
- •ABSOLUTE MAXIMUM RATINGS
- •ESD SENSITIVITY
- •TIMING SPECIFICATIONS
- •Programmable Flags Cycle Timing
- •Figure 13. Programmable Flags Cycle Timing
- •Sub-ISA Interface Read/Write Cycle Timing
- •Figure 14. Sub-ISA Interface Read Cycle Timing
- •Figure 15. Sub-ISA Interface Write Cycle Timing
- •Output Drive Currents
- •Figure 16. Typical Drive Currents
- •Power Dissipation
- •Test Conditions
- •Output Disable Time
- •Figure 17. Output Enable/Disable
- •Figure 18. Equivalent Device Loading for AC Measurements (Includes All Fixtures)
- •Figure 19. Voltage Reference Levels for AC Measurements (Except Output Enable/Disable)
- •Output Enable Time
- •Example System Hold Time Calculation
- •Capacitive Loading
- •Environmental Conditions
- •144-Lead LQFP Pinout
- •OUTLINE DIMENSIONS
- •ORDERING GUIDE

ADSP-2192M
Sub-ISA Interface Read/Write Cycle Timing
Table 36, Figure 14, and Figure 15 describe Sub-ISA Interface
Read and Write operations.
Table 36. Sub-ISA Interface Read/Write Cycle Timing
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Min |
Max |
Unit |
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tISTW |
IOR/IOW Strobe Width |
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100 |
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tICYC |
IOR/IOW Cycle Time |
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240 |
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tAESU |
AEN Setup to IOR/IOW Falling |
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10 |
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tAEHD |
AEN Hold from IOR/IOW Rising |
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0 |
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tADSU |
Address Setup to IOR/IOW Falling |
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10 |
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tADHD |
Address Hold from IOR/IOW Rising |
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0 |
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tDHD1 |
Data Hold from IOR Rising |
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20 |
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tDHD2 |
Data Hold from IOW Rising |
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15 |
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tRDDV |
IOR Falling to Valid Read Data |
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40 |
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tWDSU |
Write Data Setup to IOW Rising |
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10 |
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tRDY1 |
IOR/IOW Rising from IOCHRDY Rising |
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0 |
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tRDY2 |
IOCHRDY Falling from IOR/IOW Rising |
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20 |
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AEN |
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tAEHD |
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tAESU |
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tRDY1 |
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tRDY2 |
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IOCHRDY |
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tICYC |
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IOR |
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tISTW
tRDDV |
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tDHD1 |
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ISAD15–0
tADSU |
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tADHD |
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ISAA3–1
Figure 14. Sub-ISA Interface Read Cycle Timing
–32– |
REV. 0 |

ADSP-2192M
AEN
tAEHD
tAESU |
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tRDY1 |
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tRDY2 |
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IOCHRDY
tICYC
IOW
tSTW
tWDSU |
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tDHD2 |
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ISAD15–0
tADSU |
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tADHD |
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ISAA3–1
Figure 15. Sub-ISA Interface Write Cycle Timing
REV. 0 |
–33– |