ADSP-2192M
DSP |
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TANTALUM |
CERAMIC |
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INTERNAL |
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OR |
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CIRCUIT |
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ELECTROLYTIC |
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PCIVDD |
2.5V @ 500mA |
IVDD |
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3.0V – 5.5V |
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10µF |
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0.1µF |
ZETEX |
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VCTRLVDD |
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FZT951 |
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EXTERNAL |
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COMPONENTS |
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– |
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PCIVAUX |
+ |
3.0V – 3.6V |
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VREF |
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ZETEX |
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FZT951 |
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VCTR LAUX |
Figure 6. 2.5 V Regulator Options
Low Power Operation
In addition to supporting the PCI and USB standards’ powerdown modes, additional power-down modes for the DSP cores and peripheral buses are supported by the ADSP-2192M. The power-down modes are controlled by the DSP1 and DSP2 Inter- rupt/Power-down registers.
Clock Signals
Figure 7. Capacitor values are dependent on crystal type and should be specified by the crystal manufacturer. A parallelresonant, fundamental frequency, microprocessor-grade 24.576 MHz crystal should be used for this configuration.
3V OR 5V CLOCK
BUS SELECT
POW R ON
RESET
PCI CLO CK RUN
PCI CLO CK
PCI RESET
AC'97 BIT
CLOCK
24.576MHz
XTALI |
XTALO |
CLKSEL |
AD SP-2192M |
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BUS1 |
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BUS0 |
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P O R S T |
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CLKRUN |
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CLK |
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R S T |
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BITC LK |
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Figure 7. External Crystal Connections
The ADSP-2192M can be clocked by a crystal oscillator. If a crystal oscillator is used, the crystal should be connected across the XTALI/O pins, with two capacitors connected as shown in
USB PORT |
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1/8.192 PLL AND |
12.0MHz |
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USB |
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CLOCK RECOVERY |
CLOCK |
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DOMAIN |
X4 |
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33MHz |
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PCI CLK |
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PLL |
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PCI |
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CLOCK |
24.576MHz |
1/2 |
49.152MHz |
XTALI |
DOMAIN |
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(SUB-ISA MODE) |
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X6 |
147.456MHz |
DSP |
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CLOCK DOMAIN |
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PLL |
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(PROGRAMMABLE) |
49.152MHz |
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1/2 |
PERIPHERAL DEVICE |
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CONTROL BUS |
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CLOCK DOMAIN |
1/2 |
12.288 MHz |
AC’97 |
BITCLK |
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CLOCK DOMAIN |
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Figure 8. Clock Domains
REV. 0 |
–25– |