The DSP memory interface on the ADSP-2192M only allows reads/writes of 16-bit words. It cannot handle byte transactions. Therefore, a 64-byte maxpacketsize means 32 DSP words. A single byte cannot be transferred to/from the DSP. Endpoint 0 does not have this limitation. Because these FIFOs exist in DSP memory, the DSP shares some pointer management tasks with the USB core. For OUT transactions, the write pointer is controlled by the USB core, while the read pointer is governed by the DSP. The opposite is true for IN transactions.

Both the write and read pointers for each memory buffer would begin at zero. All USB buffers operate in a circular fashion. Once a pointer reaches the end of the buffer, it will need to be set back to zero.

OUT Transactions (Host to Device)

When an OUT transaction arrives for a particular endpoint, the USB core calculates the difference between the write and read pointers to determine the amount of room available in the FIFOs. If all of the OUT data arrives and the write pointer never catches up to the read pointer, that data is Backed and the USB core updates the Memory Buffer Write Offset register.

If at any time during the transaction the two pointers collide, the USB block responds with a NAK indicating that the host must resend the same data packet; in that case, the write pointer remains unchanged.

If for some reason the host sends more data than the maxpacketsize, the USB core accepts it, as long as there is sufficient room in the FIFO.

Because the DSP controls the read pointer, it must perform a similar calculation to determine if there is sufficient data in the FIFO to begin processing. Once The DSP has consumed some amount of data, it will need to update the Memory Buffer Read Offset register.

Table 23. Sub-ISA (PCI) Pin Descriptions

IN Transactions (Device to Host)

When an IN transaction arrives for a particular endpoint, the USB core once again computes how much read data is available in the FIFO. It also determines if the amount of read data is greater than or equal to the maxpacketsize. If both conditions are met, the USB core will transfer the data. Upon receiving ACK from the host, the USB core updates the Memory Buffer Read Offset register.

If the amount of read data is less than the maxpacketsize (a short packet), the USB core determines whether to send the data based upon a NAK count limit. This is a 4-bit field in the Endpoint Stall Policy register that can be programmed with a value indicating how many NAKs should be sent prior to transmitting a short packet. This allows flexibility in determining how IRPs are retired via short packets.

Because the DSP controls the write pointer, it must determine if there is sufficient room in the FIFO for placing new data. Once it has completed writes to the FIFO, it needs to update the Memory Buffer Write Offset register.

Sub-ISA Interface

In systems that combine the ADSP-2192M chip with other devices on a single PCI interface, the ADSP-2192M Sub-ISA mode is used to provide a simpler interface (to a PCI function ASIC), which bypasses the ADSP-2192M’s PCI interface.

In this mode, the Combo Master assumes all responsibility for interfacing the function to the PCI bus, including provision of Configuration Space registers for the ADSP-2192M system as a separate PnP function. In Sub-ISA Mode the PCI Pins are reconfigured for ISA operation as shown in Table 23.