USB Endpoint Description Register

The endpoint description register provides the USB core with information about the endpoint type, direction, and max packet size. This register is read/write by the MCU only. This register is defined for endpoints 4–11.

•PS[9:0] MAX Packet Size for endpoint

•LT[1:0] Last transaction indicator bits: 00 = Clear,

01= ACK, 10 = NAK, or 11 = ERR

•TY[1:0] Endpoint type bits: 00 = DISABLED, 01 = ISO,

10= Bulk, or 11 = Interrupt

•DR Endpoint direction bit: 1 = IN or 0 = OUT

•TB Toggle bit for endpoint. Reflects the current state of the DATA toggle bit.

USB Endpoint NAK Counter Register

This register records the number of sequential NAKs that have occurred on a given endpoint. This register is defined for endpoints 4–11. This register is read/write by the MCU only.

•N[3:0] NAK counter. Number of sequential NAKs that have occurred on a given endpoint. When N[3:0] is equal to the base NAK counter NK[3:0], a zero-length packet or packet less that maxpacketsize will be issued.

•ST 1 = Endpoint is stalled

USB Endpoint Stall Policy Register

This register contains NAK count and endpoint FIFO error policy bit. The STALL status bits for endpoints 1–3 are included as well. This register is read/write by the MCU only.

•ST[3:1] 1 = Endpoint is stalled. ST[1] maps to endpoint 1, ST[2] maps to endpoint 2, etc.

•NK[3:0] Base NAK counter. Determines how many sequential NAKs are issued before sending zero length packet on any given endpoint.

•FE FIFO error policy. 1 = When endpoint FIFO is overrun/underrun, STALL endpoint

USB Endpoint 1 Code Download Base Address Register

This register contains an 18-bit address which corresponds to the starting location for DSP code download on endpoint 1. This register is read/write by the MCU only.

USB Endpoint 2 Code Download Base Address Register

This register contains an 18-bit address which corresponds to the starting location for DSP code download on endpoint 2. This register is read/write by the MCU only.

USB Endpoint 3 Code Download Base Address Register

This register contains an 18-bit address which corresponds to the starting location for DSP code download on endpoint 3. This register is read/write by the MCU only.

USB Endpoint 1 Code Current Write Pointer Offset Register

This register contains an 18-bit address which corresponds to the current write pointer offset from the base address register for DSP code download on endpoint 1. The sum of this register and the EP1 Code Download Base Address Register represents the last DSP PM location written.

This register is read by the MCU only and is cleared to 3FFFF (–1) when the Endpoint 1 Code Download Base Address Register is updated.

USB Endpoint 2 Code Current Write Pointer Offset Register

This register contains an 18-bit address that corresponds to the current write pointer offset from the base address register for DSP code download on endpoint 2. The sum of this register and the EP2 Code Download Base Address Register represents the last DSP PM location written.

This register is read by the MCU only and is cleared to 3FFFF (–1) when the Endpoint 2 Code Download Base Address Register is updated.

USB Endpoint 3 Code Current Write Pointer Offset Register

This register contains an 18-bit address which corresponds to the current write pointer offset from the base address register for DSP code download on endpoint 3. The sum of this register and the EP3 Code Download Base Address Register represents the last DSP PM location written.

This register is read by the MCU only and is cleared to 3FFFF (–1) when the Endpoint 3 Code Download Base Address Register is updated.